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参数资料
| 型号： | ICS93V857YGT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封装： | 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-48 |
| 文件页数： | 5/9页 |
| 文件大小： | 323K |
| 代理商： | ICS93V857YGT |
5
ICS93V857
Preliminary Product Preview
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2. While the pulse skew is almost constant over frequency, the duty cycle error increases at
higher frequencies. This is due to the formula: duty cycle=twH/tc, were the cycle (tc)
decreases as the frequency goes up.
Tim ing Re quire m e nts
TA = 0 - 85C; Supply Vo ltag e AVDD, VDD = 2 .5 V +/- 0 .2 V (u n less o th erwise stated )
PARAM ETER
SYM BOL
C ONDITIONS
MIN
M AX
UNITS
Op erating clock frequency
freq op
66
170
M Hz
Input clock duty cy cle
d tin
40
60
%
C LK stab ilizatio n
TSTAB
from VDD = 3.3V to 1%
targ et freq .
100
s
Sw itching Characte ristics
PARAM ETER
SYM BOL
CONDITION
M IN
TYP
M AX
UNITS
Low-to high level p ropagatio n
delay time
tPLH
1
CLK_IN to any output
3.5
ns
High-to low level propagation
delay time
tPLL
1
CLK_IN to any output
3.5
ns
Output enable time
tEN
PD# to any output
3
ns
Output disable time
tdis
PD# to any output
3
ns
66M Hz
ps
100/125/133/167M Hz
-75
75
ps
Half-perio d jitter
t(jit_hper)
100/133/167M Hz
-100
100
Input clock slew rate
t(sir_I)
1
4
Output clock slew reate
t(sl_o)
1
4
66M Hz
ps
100/125/133/167M Hz
75
ps
Phase erro r
t(phase error)
-50
50
ps
Output to Output Skew
Tskew
100
ps
Pulse skew
Tskewp
100
ps
66M Hz to 100M Hz
49.5
50.5
%
101M Hz to 167M Hz
49
51
%
Rise Time, Fall Time
tr, tf
Load = 120
/16pF
650
800
950
ps
Jitter period
Tjit (per)
DC
2
Duty cycle
Cycle to Cycle Jitter1
Tcyc-Tcyc
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