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参数资料
| 型号： | ICS94211F-T |
| 英文描述： | Analog IC |
| 中文描述： | 模拟IC |
| 文件页数： | 13/16页 |
| 文件大小： | 232K |
| 代理商： | ICS94211F-T |
6
ICS94211
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
X
#
2
S
F
d
e
h
c
t
a
L
6
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
5
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
4
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
3
t
i
B0
41
0
M
A
R
D
S
2
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
1
t
i
B3
41
1
K
L
C
U
P
C
0
t
i
B4
41
0
K
L
C
U
P
C
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
1
)
d
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v
r
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R
(
6
t
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B7
1
F
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L
C
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P
5
t
i
B-
1
)
d
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v
r
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R
(
4
t
i
B3
11
4
K
L
C
I
C
P
3
t
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B2
11
3
K
L
C
I
C
P
2
t
i
B1
11
2
K
L
C
I
C
P
1
t
i
B0
11
1
K
L
C
I
C
P
0
t
i
B8
1
0
K
L
C
I
C
P
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
T
I
B#
N
I
PD
W
PN
O
I
T
P
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D
7
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B-
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)
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v
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R
(
6
t
i
B-
1
)
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r
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s
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R
(
5
t
i
B-
1
)
d
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v
r
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s
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R
(
4
t
i
B-
1
)
d
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v
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s
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R
(
3
t
i
B-
X
#
1
S
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d
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h
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L
2
t
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B-
1
)
d
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v
r
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s
e
R
(
1
t
i
B-
X
#
3
S
F
d
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h
c
t
a
L
0
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
Byte 4: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
6
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
5
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
4
t
i
B7
41
C
I
P
A
O
I
3
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
2
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
1
t
i
B6
41
1
F
E
R
0
t
i
B2
1
0
F
E
R
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
6
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
5
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
4
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
3
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
2
t
i
B-
1
)
e
t
o
N
(
d
e
v
r
e
s
e
R
1
t
i
B-
1
)
e
t
o
N
(
d
e
v
r
e
s
e
R
0
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Note: This is an unused register writing to this register will not
affect device performance or functinality.
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
6
t
i
B-
X
#
0
S
F
d
e
h
c
t
a
L
5
t
i
B6
21
z
H
M
8
4
t
i
B5
21
z
H
M
4
2
3
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
2
t
i
B
,
1
2
,
7
1
8
1
,
0
2
1)
2
1
:
9
(
M
A
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D
S
1
t
i
B
,
2
3
,
8
2
,
9
2
,
1
3
1)
8
:
5
(
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A
R
D
S
0
t
i
B
,
8
3
,
4
3
5
3
,
7
3
1)
4
:
1
(
M
A
R
D
S
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相关代理商/技术参数 |
参数描述 |
|---|---|
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