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参数资料
| 型号： | ICS950806YGT |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封装： | 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-56 |
| 文件页数： | 20/22页 |
| 文件大小： | 153K |
| 代理商： | ICS950806YGT |
7
ICS950806
0650A—07/30/03
Byte 0: Control Register
Notes:
1. For Byte1, Bits (3:7) refer to tables 4, 5, and 6.
2. R= Read only RW= Read and Write
3. PWD = Power on Default
4. The purpose of this bit is to allow a system designer to implement PCI_STOP functionality in one of two ways.
Wither the system designer can choose to use the externally provided PCI_STOP# pin to assert and de-assert
PCI_STOP functionality via I
2C Byte 0 Bit 3.
In Hardware mode it is not allowed to write to the I
2C Byte 0 Bit3. In Software mode it is not allowed to pull the
external PCI_STOP pin low. This avoids the issues related with Hardware started and software stopped
PCI_STOP conditions. The clock chip is to be operated in the Hardware or Software PCI_STOP mode ONLY, it
is not allowed to mix these modes.
In Hardware mode the I
2C byte 0 Bit 3 is R/W and should reflect the status of the part. Whether or not the chip
is in PCI_STOP mode.
Functionality PCI_STOP mode should be entered when [(PCI_STOP#=0) or (I
2C Byte 0 Bit 3 = 0)].
5. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high,
CPUCLKC off, and external resistor termination will bring CPUCLKC low.
Byte 1: Control Register
t
i
B#
n
i
Pe
m
a
ND
W
P
3
e
p
y
T
2
n
o
i
t
p
i
r
c
s
e
D
0
t
i
B4
50
S
FX
R
n
o
d
e
l
p
m
a
s
n
i
p
0
S
F
f
o
e
u
l
a
v
e
h
t
s
t
c
e
l
f
e
R
p
u
r
e
w
o
p
1
t
i
B5
51
S
FX
R
n
o
d
e
l
p
m
a
s
n
i
p
1
S
F
f
o
e
u
l
a
v
e
h
t
s
t
c
e
l
f
e
R
p
u
r
e
w
o
p
2
t
i
B9
33
S
FX
R
n
o
d
e
l
p
m
a
s
n
i
p
3
S
F
f
o
e
u
l
a
v
e
h
t
s
t
c
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l
f
e
R
p
u
r
e
w
o
p
3
t
i
B4
3#
P
O
T
S
_
I
C
P
3
XR
f
o
e
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l
a
v
e
h
t
s
t
c
e
l
f
e
R
:
e
d
o
m
e
r
a
w
d
r
a
H
D
W
P
n
o
d
e
l
p
m
a
s
n
i
p
#
P
O
T
S
_
I
C
P
1W
R
:
e
d
o
m
e
r
a
w
t
f
o
S
d
e
p
o
t
s
K
L
C
I
C
P
=
0
g
n
i
n
u
r
K
L
C
I
C
P
=
1
4
t
i
B5
34
S
FX
R
)
y
l
n
o
d
a
e
r
(
4
S
F
5
t
i
B5
3H
C
V
_
1
_
6
V
30
W
R
z
H
M
8
4
/
z
H
M
6
t
c
e
l
e
S
H
C
V
z
H
M
8
4
=
1
,
z
H
M
6
=
0
6
t
i
B3
35
S
F0
n
o
d
e
l
p
m
a
s
n
i
p
5
S
F
f
o
e
u
l
a
v
e
h
t
s
t
c
e
l
f
e
R
p
u
r
e
w
o
p
7
t
i
B-
d
a
e
r
p
S
d
e
l
b
a
n
E
0W
Rn
O
d
a
e
r
p
S
=
1
,
f
O
d
a
e
r
p
S
=
0
Note: For PCI_STOP#, refer to table 3
t
i
B#
n
i
Pe
m
a
ND
W
P
3
e
p
y
T
2
n
o
i
t
p
i
r
c
s
e
D
0
t
i
B1
5
,
2
5
0
T
K
L
C
U
P
C
0
C
K
L
C
U
P
C
1W
Rd
e
l
b
a
n
E
=
1
,
d
e
l
b
a
s
i
D
=
0
5
1
t
i
B8
4
,
9
4
1
T
K
L
C
U
P
C
1
C
K
L
C
U
P
C
1W
Rd
e
l
b
a
n
E
=
1
,
d
e
l
b
a
s
i
D
=
0
5
2
t
i
B4
4
,
5
4
2
T
K
L
C
U
P
C
2
C
K
L
C
U
P
C
1W
Rd
e
l
b
a
n
E
=
1
,
d
e
l
b
a
s
i
D
=
0
5
3
t
i
B1
5
,
2
5
0
C
/
T
K
L
C
U
P
C
l
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r
t
n
o
C
0W
R
f
o
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e
s
a
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t
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w
0
C
/
T
K
L
C
U
P
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ll
A
#
P
O
T
S
_
U
P
C
g
n
i
n
u
r
e
r
F
=
1
g
n
i
n
u
r
e
r
f
t
o
N
=
0
4
t
i
B5
3
,
3
31
/
0
_
6
V
31
W
R
e
d
o
m
1
/
0
_
6
V
3
g
n
i
n
u
r
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r
F
=
1
g
n
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r
f
t
o
N
=
0
5
t
i
B
,
2
,
1
2
4
2
,
3
2
5
/
4
/
3
/
2
_
6
V
31
W
R
e
d
o
m
5
/
4
/
3
/
2
_
6
V
3
g
n
i
n
u
r
e
r
F
=
1
g
n
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n
u
r
e
r
f
t
o
N
=
0
6
t
i
B8
4
,
9
4
1
C
/
T
K
L
C
U
P
C
l
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t
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o
C
0W
R
f
o
n
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r
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s
a
h
t
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w
1
C
/
T
K
L
C
U
P
C
f
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l
o
r
t
n
o
c
s
w
o
ll
A
#
P
O
T
S
_
U
P
C
g
n
i
n
u
r
e
r
F
=
1
g
n
i
n
u
r
e
r
f
t
o
N
=
0
7
t
i
B4
4
,
5
4
2
C
/
T
K
L
C
U
P
C
l
o
r
t
n
o
C
0W
R
f
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s
a
h
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C
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T
K
L
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U
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C
f
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w
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ll
A
#
P
O
T
S
_
U
P
C
g
n
i
n
u
r
e
r
F
=
1
g
n
i
n
u
r
e
r
f
t
o
N
=
0
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