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参数资料
| 型号： | ICS951901YF-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 133.34 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, MO-118, SSOP-48 |
| 文件页数： | 1/19页 |
| 文件大小： | 274K |
| 代理商： | ICS951901YF-T |
ICS951901
Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
951901 RevA -
10/22/01
Programmable Frequency Generator & Integrated Buffers for Pentium III Processor
Block Diagram
Recommended Application:
SinglechipclocksolutionforIAplatform.
Output Features:
3 - CPU @ 2.5V
13 - SDRAM @ 3.3V
6- PCI @3.3V,
2 - AGP @ 3.3V
1- 48MHz, @3.3V fixed.
1- 24/48MHz, @3.3V selectable by I
2C
(Default is 24MHz)
2- REF @3.3V, 14.318MHz.
Features:
Programmable ouput frequency.
Programmable ouput rise/fall time.
Programmable SDRAM and CPU skew.
Spread spectrum for EMI control typically
by 7dB to 8dB,
with programmable spread percentage.
Watchdog timer technology to reset system
if over-clocking causes malfunction.
Uses external 14.318MHz crystal.
FS pins for frequency select
Skew Specifications:
CPU - CPU: < 175ps
SDRAM - SDRAM < 250ps (except SDRAM12)
PCI - PCI: < 500ps
CPU (early) - PCI: 1-4ns (typ. 2ns)
Functionality
Pin Configuration
48-Pin 300mil SSOP
* These inputs have a 120K pull down to GND.
1 These are double strength.
PLL2
PLL1
Spread
Spectrum
48MHz
24_48MHz
CPUCLK (2:0)
SDRAM (12:0)
PCICLK (4:0)
AGP (1:0)
PCICLK_F
2
5
13
3
2
X1
X2
XTAL
OSC
CPU
DIVDER
SDRAM
DIVDER
PCI
DIVDER
Stop
SDATA
SCLK
FS(3:0)
PD#
PCI_STOP#
CPU_STOP#
SDRAM_STOP#
MODE
AGP_SEL
Control
Logic
Config.
Reg.
/ 2
REF(1:0)
AGP
DIVDER
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
VDDA
(AGPSEL)REF0
*(FS3)REF1
GND
X1
X2
VDDPCI
*(FS1)PCICLK_F
*(FS2)PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
GND
VDDAGP
AGPCLK0
AGPCLK1
GND
*(FS0)48MHz
*(MODE)24_48MHz
VDD48
SDATA
SCLK
1
*
VDDL
CPUCLK0
CPUCLK1
CPUCLK2
GND
VDDSDR
SDRAM0
SDRAM1
SDRAM2
GND
SDRAM3
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
GND
SDRAM8/PD#
SDRAM9/SDRAM_STOP#
GND
SDRAM10/PCI_STOP#
SDRAM11/CPU_STOP#
SDRAM12
VDDSDR
ICS9519
01
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
FS3
FS2
FS1
FS0
CPU
SDRAM
PCI
AGP1
AGP0
Bit7
Bit6
Bit5
Bit4
MHz
SEL=1
SEL=0
0
66.67
33.33
66.67
64
0
1
66.67
100.00
33.33
66.67
64
0
1
0
66.67
133.34
33.33
66.67
64
0
1
75.00
37.50
75.00
64
0
1
0
83.31
33.32
66.64
64
0
1
0
1
90.00
30.00
60.00
64
0
1
0
95.00
31.67
63.33
64
0
1
100.00
66.67
33.33
66.67
64
0
1
0
100.00
33.33
66.67
64
0
1
0
1
100.00
133.34
33.33
66.67
64
0
1
0
1
0
105.00
35.00
70.00
64
0
1
0
1
112.00
33.60
67.20
64
0
1
0
117.99
35.40
70.80
64
0
1
0
1
124.09
31.02
62.05
64
0
1
0
133.34
100.00
33.33
66.67
64
0
1
111
133.34
33.33
66.67
64
Bit2
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