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参数资料
| 型号： | ICS951901YF-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 133.34 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, MO-118, SSOP-48 |
| 文件页数： | 12/19页 |
| 文件大小： | 274K |
| 代理商： | ICS951901YF-T |
2
ICS951901
Third party brands and names are the property of their respective owners.
General Description
Pin Configuration
The ICS951901 is a single chip clock solution for desktop designs
using 630S chipsets. It provides all necessary clock signals for such
a system.
The ICS951901 belongs to ICS new generation of programmable
systemclockgenerators.ItemploysserialprogrammingI2Cinterface
asavehicleforchangingoutputfunctions,changingoutputfrequency,
configuringoutputstrength,configuringoutputtooutputskew,changing
spread spectrum amount, changing group divider ratio and dis/
enabling individual clocks. This device also has ICS propriety
'Watchdog Timer' technology which will reset the frequency
to a safe setting if the system becomes unstable from over
clocking.
Power Groups
Analog
VDDA = X1, X2, Core, PLL
VDD48 = 48MHz, 24MHz, fixed PLL
Digital
VDDPCI = PCICLK_F, PCICLK
VDDSDR = SDRAM
VDDAGP=AGP, REF
E
D
O
M
1
2
n
i
P
7
2
n
i
P8
2
n
i
P0
3
n
i
P1
3
n
i
P
01
1
M
A
R
D
S0
1
M
A
R
D
S9
M
A
R
D
S8
M
A
R
D
S
1#
P
O
T
S
_
U
P
C#
P
O
T
S
_
I
C
P#
P
O
T
S
_
M
A
R
D
S#
D
P
MODE Pin Power Management Control Input
PIN NUMBER
PIN NAME
TYPE
DESCRIPTIO N
1, 7, 15, 22, 25,
35, 43
VDD
PWR
3.3V Power supply for SDRAM output buffers, PCI output buffers,
reference output buffers and 48MHz output
AGPSEL
IN
AGP frequency select pin.
REF0
OUT
14.318 MHz reference clock.
FS3
IN
Frequency select pin.
REF1
OUT
14.318 MHz reference clock.
4, 14, 18, 19, 29,
32, 39, 44
GND
PWR
Ground pin for 3V outputs.
5
X1
IN
Crystal input,nominally 14.318MHz.
6
X2
OUT
Crystal output, nom inally 14.318MHz.
FS1
IN
Frequency select pin.
PCICLK_F
OUT
PCI clock output, not affected by PCI_STOP#
FS2
IN
Frequency select pin.
PCICLK0
OUT
PCI clock output.
13, 12, 11, 10
PCICLK (4:1)
OUT
PCI clock outputs.
17, 16,
AGP (1:0)
OUT
AGP outputs defined as 2X PCI. These m ay not be stopped.
FS0
IN
Frequency select pin.
48MHz
OUT
48MHz output clock
MODE
IN
Pin 27, 28, 30, & 31 function select pin
0=Desktop 1=Mobile m ode
24_48MHz
OUT
Clock output for super I/O/USB default is 24MHz
23
SDATA
I/O
Data pin for I
2C circuitry 5V tolerant
24
SCLK
IN
Clock pin of I
2C circuitry 5V tolerant
CPU_STOP#
IN
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when
input is low and MODE pin is in Mobile m ode
SDRAM11
OUT
SDRAM clock output
PCI_STOP#
IN
Stops all CPUCLKs clocks at logic 0 level, when input is low and MODE
pin is in Mobile mode
SDRAM10
OUT
SDRAM clock output
SDRAM9
OUT
SDRAM clock output
SDRAM_STOP#
IN
Stops all SDRAM clocks at logic 0 level, when input is low and MODE pin
is in Mobile mode
PD#
IN
Asynchronous active low input pin used to power down the device into a
low power state. The internal clocks are disabled and the VCO and the
crystal are stopped. The latency of the power down will not be greater than
3ms.
SDRAM8
OUT
SDRAM clock output
26 33, 34, 36, 37,
38, 40, 41, 42
SDRAM (12, 7:0)
OUT
SDRAM clock outputs
45, 46, 47
CPUCLK (2:0)
OUT
CPU clock outputs.
48
VDDL
PWR
Power pin for the CPUCLKs. 2.5V
31
20
2
8
9
21
3
30
27
28
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相关代理商/技术参数 |
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