参数资料
型号: ICS952607YFLF-T
元件分类: 时钟产生/分配
英文描述: 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封装: LEAD FREE, MO-118, SSOP-48
文件页数: 3/22页
文件大小: 204K
代理商: ICS952607YFLF-T
11
Integrated
Circuit
Systems, Inc.
ICS952607
0734A—07/26/05
Table 4: Mode Selection Table
Mode
Standard Overclock Mode
CPU Overclock Mode
Graphic Overclock Mode
IIC Control
Byte 5 bit(6:5) = 00
Byte 5 bit(6:5) = 01
Byte 5 bit(6:5) = 10
CPU M/N Overclocking
Byte 11 & 12
SRC M/N Overclocking
Byte 11 & 12
Byte 5 & 6 (asynchronous)
Byte 11 & 12
AGP/PCI M/N Overclocking
Byte 11 & 12
Byte 5 & 6 (asynchronous)
Spreading
All clocks have spread.
Only CPU clocks have spread.
Latch input shoud be set as FS(4:0)
= 10xxx. CPU & SRC have spread.
Remark
All clocks oveclock together by Byte
11&12 M/N programming.
CPU overclock by Byte 11&12
SRC/AGP/PCI overclock by Byte
5&6 asynchronously.
CPU/SRC overclock by Byte 11&12
AGP/PCI overclock by Byte 5&6
asynchronously.
Mode B (B6&B3 bit 7) AGP/PCI can
be selected to be overclock from 66/33,
72/36 or 80/40.
Simple async AGP/PCI overclocking
w/o using M/N programming.
SRC can be kept at 100 w/o spread
yet AGP/PCI can be overclocked.
Simple async AGP/PCI overclocking
w/o using M/N programming.
Table 5: Asynchronous 3V66/PCI Frequency Table
Byte6 Bit7
Byte3 Bit7
3V66/PCI Frequency
0
66.66/33.33
0
1
80.00/40.00
1
0
72.73/36.36
I
2C Table: Vendor & Revision ID Register
Control
Function
Bit 7
ASEL0
3V66/PCI Freq Select
RW
0
Bit 6
N PLL2 Div6
RW
X
Bit 5
N PLL2 Div5
RW
X
Bit 4
N PLL2 Div4
RW
X
Bit 3
N PLL2 Div3
RW
X
Bit 2
N PLL2 Div2
RW
X
Bit 1
N PLL2 Div1
RW
X
Bit 0
N PLL2 Div0
RW
X
I
2C Table: Vendor & Revision ID Register
Control
Function
Bit 7
RID3
R
X
Bit 6
RID2
R
X
Bit 5
RID1
R
X
Bit 4
RID0
R
X
Bit 3
VID3
R
0
Bit 2
VID2
R
0
Bit 1
VID1
R
0
Bit 0
VID0
R
1
I
2C Table: Byte Count Register
Control
Function
Bit 7
BC7
RW
0
Bit 6
BC6
RW
0
Bit 5
BC5
RW
0
Bit 4
BC4
RW
0
Bit 3
BC3
RW
1
Bit 2
BC2
RW
1
Bit 1
BC1
RW
1
Bit 0
BC0
RW
1
--
1
--
1
Writing to this register will configure how
many bytes will be read back, default is 0F =
15 bytes.
0
The decimal representation of N PLL2 Div
(6:0) + 8 is equal to VCO divider value for
PLL2.
01
Byte 6
Pin #
Name
-
PWD
-
N Divider Programming
bits for Async mode 2&3
-
See Table 4: Async AGP/PCI Freq Table
PWD
-
Byte Count
Programming b(7:0)
-
Type
-
Type
-
VENDOR ID
-
Name
Byte 8
Pin #
PWD
-
REVISION ID
-
Byte 7
Pin #
Name
0
Type
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