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参数资料
| 型号： | ICS952607YFLF-T |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | LEAD FREE, MO-118, SSOP-48 |
| 文件页数： | 4/22页 |
| 文件大小： | 204K |
| 代理商： | ICS952607YFLF-T |
12
Integrated
Circuit
Systems, Inc.
ICS952607
0734A—07/26/05
I
2C Table: Watchdog Timer Register
Control
Function
Bit 7
WD7
WD Timer Bit 7
RW
0
Bit 6
WD6
WD Timer Bit 6
RW
0
Bit 5
WD5
WD Timer Bit 5
RW
0
Bit 4
WD4
WD Timer Bit 4
RW
0
Bit 3
WD3
WD Timer Bit 3
RW
1
Bit 2
WD2
WD Timer Bit 2
RW
0
Bit 1
WD1
WD Timer Bit 1
RW
1
Bit 0
WD0
WD Timer Bit 0
RW
1
I
2C Table: VCO Control Select Bit & WD Timer Control Register
Control
Function
Bit 7
M/NEN
M/N Programming
Enable
RW
0
Bit 6
WDEN
Watchdog Enable
R
1
Bit 5
WDFSEN
WD Safe Frequency
Mode
RW
0
Bit 4
WD SF4
RW
0
Bit 3
WD SF3
RW
0
Bit 2
WD SF2
RW
0
Bit 1
WD SF1
RW
0
Bit 0
WD SF0
RW
0
I
2C Table: VCO Frequency Control Register
Control
Function
Bit 7
N Div8
N Divider Prog bit 8
RW
X
Bit 6
M Div6
RW
X
Bit 5
M Div5
RW
X
Bit 4
M Div4
RW
X
Bit 3
M Div3
RW
X
Bit 2
M Div2
RW
X
Bit 1
M Div1
RW
X
Bit 0
M Div0
RW
X
I
2C Table: VCO Frequency Control Register
Control
Function
Bit 7
N Div7
RW
X
Bit 6
N Div6
RW
X
Bit 5
N Div5
RW
X
Bit 4
N Div4
RW
X
Bit 3
N Div3
RW
X
Bit 2
N Div2
RW
X
Bit 1
N Div1
RW
X
Bit 0
N Div0
RW
X
I
2C Table: Spread Spectrum Control Register
Control
Function
Bit 7
SSP7
RW
X
Bit 6
SSP6
RW
X
Bit 5
SSP5
RW
X
Bit 4
SSP4
RW
X
Bit 3
SSP3
RW
X
Bit 2
SSP2
RW
X
Bit 1
SSP1
RW
X
Bit 0
SSP0
RW
X
01
PWD
01
Disable
Enable
PWD
01
Byte 9
Pin #
Name
Type
Disable
Enable
Latched FS/Byte0
0
These Spread Spectrum bits in Byte 13 and
14 will program the spread pecentage. It is
recommended to use ICS Spread % table for
spread programming.
These bits represent X*290ms the watchdog
timer waits before it goes to alarm mode.
Default is 11 x 293ms = 3.2s.
Writing to these bit will configure the safe
frequency as Byte0 bit (4:0).
The decimal representation of M and N
Divier in Byte 11 and 12 will configure the
VCO frequency. Default at power up = latch-
in or Byte 0 Rom table. VCO Frequency =
14.318 x [NDiv(8:0)+8] / [MDiv(6:0)+2]
WD B10 b(4:0)
1
The decimal representation of M and N
Divier in Byte 11 and 12 will configure the
VCO frequency. Default at power up = latch-
in or Byte 0 Rom table. VCO Frequency =
14.318 x [NDiv(8:0)+8] / [MDiv(6:0)+2]
PWD
-
Spread Spectrum
Programming b(7:0)
-
Name
Type
-
Byte 13
Pin #
PWD
-
N Divider Programming
b(8:0)
-
Byte 12
Pin #
Name
Type
-
M Divider Programming
bits
-
Byte 11
Pin #
Name
Type
-
Watch Dog Safe Freq
Programming bits
-
PWD
-
Byte 10
Pin #
Name
Type
-
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