参数资料
型号: ICS95V857CG
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟及定时
英文描述: 95V SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
封装: 0.240 INCH, TSSOP-48
文件页数: 12/15页
文件大小: 215K
代理商: ICS95V857CG
6
ICS95V857-XXX
Preliminary Product Preview
0674I—03/28/03
Notes:
1.
Refers to transition on noninverting output in PLL bypass mode.
2.
While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies.This is due to the formula: duty cycle=twH/tc, where
the cycle (tc) decreases as the frequency goes up.
3.
Switching characteristics guaranteed for application frequency range.
4.
Static phase offset shifted by design.
Timing Requirements
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Max clock frequency
freqop
2.5V+0.2V @ 25
oC
33
233
MHz
Application Frequency
Range
freqApp
2.5V+0.2V @ 25
oC
95
170
MHz
Input clock duty cycle
dtin
40
60
%
CLK stabilization
TSTAB
100
s
Switching Characteristics
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
Low-to high level
propagation delay time
tPLH
1
CLK_IN to any output
5.5
ns
High-to low level propagation
delay time
tPLL
1
CLK_IN to any output
5.5
ns
Output enable time
tEN
PD# to any output
5
ns
Output disable time
tdis
PD# to any output
5
ns
Period jitter
Tjit (per)
100/125/133/167/200MHz
-40
40
ps
Half-period jitter
t(jit_hper)
100/133/167/200MHz
-50
50
ps
Input clock slew rate
tsl(i)
14
V/ns
Output clock slew rate
tsl(o)
12.5
V/ns
Cycle to Cycle Jitter
1
Tcyc-Tcyc
100/125/133/167/200MHz
50
ps
Phase error
t(phase error)
4
-50
0
50
ps
Output to Output Skew
Tskew
30
ps
Duty cycle
DC
2
100MHz to 200MHz
49.5
50.5
%
Rise Time, Fall Time
tr, tf
Load = 120
/16pF
650
800
950
ps
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