参数资料
型号: ICS97ULP877AHT
厂商: IDT, Integrated Device Technology Inc
文件页数: 7/14页
文件大小: 0K
描述: IC CLOCK DRIVER 1.8V LP 52-BGA
产品变化通告: Product Discontinuation 09/Dec/2011
标准包装: 2,500
类型: 时钟缓冲器/驱动器,零延迟缓冲器,多路复用器
PLL:
主要目的: 存储器,DDR2
输入: 时钟
输出: SSTL-18
电路数: 1
比率 - 输入:输出: 1:10
差分 - 输入:输出: 是/是
频率 - 最大: 410MHz
电源电压: 1.7 V ~ 1.9 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 52-VFBGA
供应商设备封装: 52-CABGA(4.5x7.0)
包装: 带卷 (TR)
其它名称: 97ULP877AHT
2
ICS97ULP877A
7116—03/27/07
Pin Descriptions
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The PLL clock buffer, ICS97ULP877A, is designed for a VDDQ of 1.8 V, a AVDD of 1.8 V and differential data input and
output levels. Package options include a plastic 52-ball VFBGA and a 40-pin MLF.
ICS97ULP877A is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to ten
differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock outputs (FB_OUTT,
FBOUTC). The clock outputs are controlled by the input clocks (CLK_INT, CLK_INC), the feedback clocks (FB_INT,
FB_INC), the LVCMOS program pins (OE, OS) and the Analog Power input (AVDD).When OE is low, the outputs (except
FB_OUTT/FB_OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency. OS (Output
Select) is a program pin that must be tied to GND or VDDQ.When OS is high, OE will function as described above.When
OS is low, OE has no effect on CLKT7/CLKC7 (they are free running in addition to FB_OUTT/FB_OUTC).When AVDD
is grounded, the PLL is turned off and bypassed for test purposes.
When both clock signals (CLK_INT, CLK_INC) are logic low, the device will enter a low power mode. An input logic
detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform
a low power state where all outputs, the feedback and the PLL are OFF.When the inputs transition from both being logic
low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL
will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input clock pair (CLK_INT, CLK_INC)
within the specified stabilization time tSTAB.
The PLL in ICS97ULP877A clock driver uses the input clocks (CLK_INT, CLK_INC) and the feedback clocks (FB_INT,
FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT[0:9], CLKC[0:9]).
ICS97ULP877A is also able to track Spread Spectrum Clocking (SSC) for reduced EMI.
ICS97ULP877A is characterized for operation from 0°C to 70°C.
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