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参数资料
| 型号： | ICSSSTUAH32865A |
| 厂商： | Integrated Device Technology, Inc. |
| 英文描述： | 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| 中文描述： | 25位可配置注册缓冲内存 |
| 文件页数： | 10/17页 |
| 文件大小： | 351K |
| 代理商： | ICSSSTUAH32865A |
IDT74SSTUBH32865A
28-BIT 1:2 REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
28-BIT 1:2 REGISTERED BUFFER FOR DDR2
10
IDT74SSTUBH32865A
7103/10
Timing Requirements Over Recommended Operating Free-Air Temperature
Range
Switching Characteristics Over Recommended Free Air Operating Range
(unless otherwise noted)
Symbol
f
CLOCK
t
W
t
ACT
t
INACT
Parameter
Clock Frequency
Pulse Duration; CLK, CLK HIGH or LOW
Differential Inputs Active Time
1
Differential Inputs Inactive Time
2
DCS0 before CLK
↑
, CLK
↓
, DCS and CSGateEN
HIGH; DCS1 before CLK
↑
, CLK
↓
, DCS0 and
CSGateEN HIGH
DCSn, DODT, DCKE, and Dn after CLK
↑
, CLK
↓
PARIN after CLK
↑
, CLK
↓
DCSn, DODT, DCKE, and Dn after CLK
↑
, CLK
↓
PARIN after CLK
↑
, CLK
↓
V
DD
= 1.8V ± 0.1V
Min.
Units
MHz
ns
ns
ns
Max.
410
1
1
minimum time of t
ACT
(max) after RESET is taken HIGH.
2
V
REF
, data, and clock inputs must be held at a valid input voltage levels (not floating) for a minimum
time of t
INACT
(max) after RESET is taken LOW.
V
REF
must be held at a valid input voltage level and data inputs must be held at valid logic levels for a
10
15
t
SU
Setup
Time
0.6
ns
0.5
0.5
0.4
0.4
t
H
Hold
Time
ns
Symbol
f
MAX
t
PDM1
t
PDQ2
t
PDMSS1
t
LH
t
HL
t
PHL
t
PLH
Parameter
Max Input Clock Frequency
Propagation Delay, single bit switching, CLK
↑
to CLK
↓
to Qn
Propagation Delay, single-bit switching, CLK
↑
/ CLK
↓
to Qn
Propagation Delay, simultaneous switching, CLK
↑
to CLK
↓
to Qn
LOW to HIGH Propagation Delay, CLK
↑
to CLK
↓
to PTYERR
HIGH to LOW Propagation Delay, CLK
↑
to CLK
↓
to PTYERR
HIGH to LOW Propagation Delay, RESET
↓
to Qn
↓
LOW to HIGH Propagation Delay, RESET
↓
to PTYERR
↑
V
DD
= 1.8V ± 0.1V
Min.
410
1.1
0.4
Units
MHz
ns
ns
ns
ns
ns
ns
ns
Max.
1
2
Design target as per JEDEC specifications.
Production Test. (See Production Test Circuit in TEST CIRCUIT AND WAVEFORM section.)
1.6
0.8
1.7
3
3
3
3
1.2
1
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| ICSSSTUAH32865AHLFT | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAH32868A | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAH32868AHLF | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUB32864A | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:25-Bit Configurable Registered Buffer for DDR2 |
| ICSSSTUB32864AZ(LF)T | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:25-Bit Configurable Registered Buffer for DDR2 |
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