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参数资料
| 型号： | ICSSSTV16857CYLLF-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | LOW SKEW CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封装： | 4.40 MM, 0.40 MM PITCH, MO-153, TVSOP-48 |
| 文件页数： | 5/8页 |
| 文件大小： | 81K |
| 代理商： | ICSSSTV16857CYLLF-T |
5
ICSSSTV16857C
Third party brands and names are the property of their respective owners.
T iming Re quire me nts
(over recom m ended operating free-air tem perature range, unless otherwis e noted)
SYMBO L
PAR AMETERS
VD D=2.5±0.2V
UNITS
MIN
TYP
MAX
fclock
C loc k frequency
133
200
MHz
tPD
C loc k to output tim e
1.6
2
2.6
ns
tRST
R eset to output tim e
2.5
2.7
3.3
ns
tSL
O utput slew rate
1
1.5
4
V/ns
Setup tim e, fast slew rate
2, 4
Data before C K
! ,CK#"
0.75
0.018
ns
tSU
Setup tim e, s low slew rate
3, 4
0.9
ns
Hold tim e, fas t slew rate
2,4
Data after CK
! ,CK#"
0.75
0.145
ns
Th
Hold tim e, slow s lew rate
3 , 4
0.9
ns
Notes:
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate ?1V/ns.
4 - CLK, C LK# signals input slew rates are ?1V/ns.
3 - For data signal input slew rate ?0.5V/ns and < 1V/ns .
Switching C haracte ristics
(over rec om m ended operating free-air tem perature range, unles s otherw is e noted)
S YMB O L
From
To
VD D = 2.5±0.2V
UNITS
(Input)
(O utput)
MIN
TYP
MAX
fclock
133
200
MHz
tPD
CLK , CLK#
Q
1.6
2
2.6
ns
tph1
R ESET
Q
2.5
2.7
3.3
ns
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICSSSTV16857YG-T | 制造商:ICS 制造商全称:ICS 功能描述:DDR 14-Bit Registered Buffer |
| ICSSSTV16857YL-T | 制造商:ICS 制造商全称:ICS 功能描述:DDR 14-Bit Registered Buffer |
| ICSSSTV16859 | 制造商:ICS 制造商全称:ICS 功能描述:DDR 13-Bit to 26-Bit Registered Buffer |
| ICSSSTV16859CG-T | 制造商:ICS 制造商全称:ICS 功能描述:DDR 13-Bit to 26-Bit Registered Buffer |
| ICSSSTV16859YG-T | 制造商:ICS 制造商全称:ICS 功能描述:DDR 13-Bit to 26-Bit Registered Buffer |
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