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参数资料
| 型号： | ICSSSTV16857YLLF-T |
| 元件分类： | 锁存器 |
| 英文描述： | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48 |
| 封装： | 0.173 INCH, 0.40 MM PITCH, TVSOP-48 |
| 文件页数： | 2/8页 |
| 文件大小： | 114K |
| 代理商： | ICSSSTV16857YLLF-T |
2
ICSSSTV16857
Third party brands and names are the property of their respective owners.
General Description
Pin Configuration
The 14-bit ICSSTV16857 is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2 I/O Levels
except for the RESET# input which is LVCMOS.
Data flow from D to Q is controlled by the differential clock, CLK, CLK# and RESET#. Data is triggered on the
positive edge of CLK. CLK# must be used to maintain noise margins. RESET# must be supported with LVCMOS
levels as VREF may not be stable during power-up. RESET# is asynchronous and is intended for power-up only and
when low assures that all of the registers reset to the Low State, Q outputs are low, and all input receivers, data and
clock are switched off.
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相关PDF资料 |
PDF描述 |
|---|---|
| ICSSSTV16859CG-T | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO64 |
| SSTV16859CKLF | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CQCC56 |
| ICSSSTV16859YKLF | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CQCC56 |
| ICSSSTV32852AHLF | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA114 |
| ICSSSTVA16857YG-T | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICSSSTV16857YL-T | 制造商:ICS 制造商全称:ICS 功能描述:DDR 14-Bit Registered Buffer |
| ICSSSTV16859 | 制造商:ICS 制造商全称:ICS 功能描述:DDR 13-Bit to 26-Bit Registered Buffer |
| ICSSSTV16859CG-T | 制造商:ICS 制造商全称:ICS 功能描述:DDR 13-Bit to 26-Bit Registered Buffer |
| ICSSSTV16859YG-T | 制造商:ICS 制造商全称:ICS 功能描述:DDR 13-Bit to 26-Bit Registered Buffer |
| ICSSSTV16859YK | 制造商:ICS 制造商全称:ICS 功能描述:DDR 13-Bit to 26-Bit Registered Buffer |
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