- 您现在的位置：买卖IC网 > PDF目录65536 > ICSSSTV16857YLLF-T SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48 PDF资料下载
参数资料
| 型号： | ICSSSTV16857YLLF-T |
| 元件分类： | 锁存器 |
| 英文描述： | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48 |
| 封装： | 0.173 INCH, 0.40 MM PITCH, TVSOP-48 |
| 文件页数： | 6/8页 |
| 文件大小： | 114K |
| 代理商： | ICSSSTV16857YLLF-T |
6
ICSSSTV16857
Third party brands and names are the property of their respective owners.
Notes: 1. CL incluces probe and jig capacitance.
2. IDD tested with clock and data inputs held at VDD or GND, and Io = 0mA.
3. All input pulses are supplied by generators having the following chareacteristics: PRR
≤10 MHz, Zo=50, input
slew rate = 1 V/ns ±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per measurement.
5. VTT = VREF = VDDQ/2
6. VIH = VREF + 310mV (ac voltage levels) for differential inputs. VIH = VDD for LVCMOS input.
7. VIL = VREF -310mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input.
8. tPLH and tPHL are the same as tpd
Test Point
Load Circuit
From Output
Under Test
C = 30 pF
(see Note 1)
L
VTT
R =
L 50W
LVCMOS
RESET#
Input
LVCMOS
RESET#
Input
V/2
DD
tinact
tact
I
(see note 2)
DD
IDDH
IDDL
10%
90%
Voltage and Current Waveforms
Inputs Active and Inactive Times
Voltage Waveforms - Propagation Delay Times
Parameter Measurement Information (V
= 2.5V ±0.2V)
DD
Voltage Waveforms - Pulse Duration
Voltage Waveforms - Setup and Hold Times
V/2
DD
VDD
0V
tw
tSU
th
VIH
VOH
VTT
VOH
VIH
VIL
VOL
VI(pp)
VIL
VREF
VICR
tPHL
V/2
DD
VICR
Input
Timing
Input
Timing
Input
Output
相关PDF资料 |
PDF描述 |
|---|---|
| ICSSSTV16859CG-T | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO64 |
| SSTV16859CKLF | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CQCC56 |
| ICSSSTV16859YKLF | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CQCC56 |
| ICSSSTV32852AHLF | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA114 |
| ICSSSTVA16857YG-T | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICSSSTV16857YL-T | 制造商:ICS 制造商全称:ICS 功能描述:DDR 14-Bit Registered Buffer |
| ICSSSTV16859 | 制造商:ICS 制造商全称:ICS 功能描述:DDR 13-Bit to 26-Bit Registered Buffer |
| ICSSSTV16859CG-T | 制造商:ICS 制造商全称:ICS 功能描述:DDR 13-Bit to 26-Bit Registered Buffer |
| ICSSSTV16859YG-T | 制造商:ICS 制造商全称:ICS 功能描述:DDR 13-Bit to 26-Bit Registered Buffer |
| ICSSSTV16859YK | 制造商:ICS 制造商全称:ICS 功能描述:DDR 13-Bit to 26-Bit Registered Buffer |
发布紧急采购，3分钟左右您将得到回复。