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参数资料
| 型号： | ICSSSTVA16859CK-LF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 锁存器 |
| 英文描述： | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, QCC56 |
| 封装： | MLF-56 |
| 文件页数： | 5/12页 |
| 文件大小： | 238K |
| 代理商： | ICSSSTVA16859CK-LF |
2
ICSSSTVF16859
Advance Information
0776—03/18/03
General Description
Pin Configuration (64-Pin TSSOP)
The 13-bit-to-26-bit ICSSSTVF16859 is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2
I/O levels, except for the LVCMOS RESET# input.
Data flow from D to Q is controlled by the differential clock (CLK/CLK#) and a control signal (RESET#). The positive
edge of CLK is used to trigger the data flow and CLK# is used to maintain sufficient noise margins where as RESET#,
an LVCMOS asynchronous signal, is intended for use at the time of power-up only. ICSSSTVF16859 supports low-
power standby operation. A logic level “Low” at RESET# assures that all internal registers and outputs (Q) are reset
to the logic “Low” state, and all input receivers, data (D) and clock (CLK/CLK#) are switched off. Please note that
RESET# must always be supported with LVCMOS levels at a valid logic state because VREF may not be stable during
power-up.
To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESET# must be held
at a logic “Low” level during power up.
In the DDR DIMM application, RESET# is specified to be completely asynchronous with respect to CLK and CLK#.
Therefore, no timing relationship can be guaranteed between the two signals. When entering a low-power standby state,
the register will be cleared and the outputs will be driven to a logic “Low” level quickly relative to the time to disable
the differential input receivers. This ensures there are no glitches on the output. However, when coming out of low-power
standby state, the register will become active quickly relative to the time to enable the differential input receivers. When
the data inputs are at a logic level “Low” and the clock is stable during the “Low”-to-”High” transition of RESET# until
the input receivers are fully enabled, the design ensures that the outputs will remain at a logic “Low” level.
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Pin Configuration (56-Pin MLF2)
相关PDF资料 |
PDF描述 |
|---|---|
| ICSSSTVA16859CK | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, QCC56 |
| ICSSSTVA16859CGLF-T | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO64 |
| ICSSSTVA16859CKLF | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, QCC56 |
| ICSSTV16859BG-T | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO64 |
| ICSSTV16859BG-LF-T | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO64 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICSSSTVF16859 | 制造商:ICS 制造商全称:ICS 功能描述:DDR 13-Bit to 26-Bit Registered Buffer |
| ICSSSTVF16859BKLFT | 制造商:ICS 功能描述: |
| ICSSSTVF16859BKT | 制造商:ICS 功能描述: |
| ICSSSTVF16859YK | 制造商:ICS 制造商全称:ICS 功能描述:DDR 13-Bit to 26-Bit Registered Buffer |
| ICSS-VE-PU-N | 制造商:Black Box Corporation 功能描述:iCOMPEL S Series VESA Publisher |
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