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参数资料
| 型号： | ICSVF2509YGLN-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 2509 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封装： | 4.40 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-24 |
| 文件页数： | 2/7页 |
| 文件大小： | 121K |
| 代理商： | ICSVF2509YGLN-T |
2
ICSVF2509B
1036C—07/13/05
Pin Descriptions
Functionality
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1
AGND
PWR
Analog Ground
2, 10, 15
VCC
PWR
Power Supply (3.3V)
3
CLKA0
OUT
Buffered clock output, Bank A
4
CLKA1
OUT
Buffered clock output, Bank A
5
CLKA2
OUT
Buffered clock output, Bank A
6, 7, 18, 19
GND
PWR
Ground
8
CLKA3
OUT
Buffered clock output, Bank A
9
CLKA4
OUT
Buffered clock output, Bank A
11
OEA
1
IN
Output enable (has internal pull_up). When high, normal
operation. When low bank A clock outputs are disabled to a
logic low state.
12
FBOUT
OUT
Feedback output
13
FBIN
IN
Feedback input
14
OEB
1
IN
Output enable (has internal pull_up). When high, normal
operation. When low bank B clock outputs are disabled to a
logic low state.
16
CLKB3
OUT
Buffered clock output. Bank B
17
CLKB2
OUT
Buffered clock output. Bank B
20
CLKB1
OUT
Buffered clock output. Bank B
21
CLKB0
OUT
Buffered clock output. Bank B
22
VCC
PWR
Power Supply (3.3V) digital supply.
23
AVCC
IN
Analog power supply (3.3V). When input is ground PLL is off
and bypassed.
24
CLKIN
IN
Clock input
OEA
OEB
AVCC
CLKA
(0:4)
CLKB
(0:3)
FBOUT
Source
00
3.33
00
Driven
PLL
N
0
1
3.33
0
Driven
PLL
N
1
0
3.33
Driven
0
Driven
PLL
N
1
3.33
Driven
PLL
N
00000
Driven
CLKIN
Y
0100
Driven
CLKIN
Y
100
Driven
0
Driven
CLKIN
Y
110
Driven
CLKIN
Y
Test mode:
When AVCC is 0, shuts off the PLL and connects the input directly to the output buffers
Buffer Mode
INPUTS
OUTPUTS
PLL
Shutdown
Note:
1.
Weak pull-ups on these inputs
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