![](http://datasheet.mmic.net.cn/30000/MQ80C32-12SBR_datasheet_2377008/MQ80C32-12SBR_21.png)
21
AT90PWM216/316 [DATASHEET]
7710H–AVR–07/2013
The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the
Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software con-
tains a Boot Loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2
Boot programming.
Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write
Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the
EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to
have the Global Interrupt Flag cleared during all the steps to avoid these problems.
When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit
and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before
the next instruction is executed.
Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in
the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read
access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the
CPU is halted for four cycles before the next instruction is executed.
The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither
possible to read the EEPROM, nor to change the EEAR Register.
The calibrated Oscillator is used to time the EEPROM accesses.
Table 5-2 lists the typical programming time for
EEPROM access from the CPU.
The following code examples show one assembly and one C function for writing to the EEPROM. The examples
assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during
execution of these functions. The examples also assume that no Flash Boot Loader is present in the software. If
such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.
Table 5-2.
EEPROM Programming Time.
Symbol
Number of Calibrated RC Oscillator Cycles
Typ Programming Time
EEPROM write
(from CPU)
26368
3.3 ms