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参数资料
| 型号： | IDT23S09T-1DCG |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 23S SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封装： | GREEN, SOIC-16 |
| 文件页数： | 2/6页 |
| 文件大小： | 53K |
| 代理商： | IDT23S09T-1DCG |
2
COMMERCIALTEMPERATURERANGE
IDT23S09T
2.5VZERODELAYCLOCKBUFFER,SPREADSPECTRUMCOMPATIBLE
PIN CONFIGURATION
SOIC
TOP VIEW
Symbol
Rating
Max.
Unit
VDD
Supply Voltage Range
–0.5 to +4.6
V
VI(2)
Input Voltage Range (REF)
–0.5 to +5.5
V
VI
InputVoltageRange
–0.5 to
V
(except REF)
VDD+0.5
IIK (VI < 0)
Input Clamp Current
–50
mA
IO (VO = 0 to VDD)
ContinuousOutputCurrent
±50
mA
VDD or GND
ContinuousCurrent
±100
mA
TA = 55°C
Maximum Power Dissipation
0.7
W
(in still air)(3)
TSTG
StorageTemperatureRange
–65 to +150
° C
Operating
CommercialTemperature
0 to +70
° C
Temperature
Range
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
of 150°C and a board trace length of 750 mils.
NOTES:
1. Weak pull down.
2. Weak pull down on all outputs.
3. Weak pull ups on these inputs.
PIN DESCRIPTION
ABSOLUTE MAXIMUM RATINGS(1)
Pin Name
Pin Number
Type
Functional Description
REF(1)
1
I N
Input reference clock, 3.3V tolerant input
CLKA1(2)
2
Out
Output clock for bank A
CLKA2(2)
3
Out
Output clock for bank A
VDD
4, 13
PWR
2.5V Supply
GND
5, 12
GND
Ground
CLKB1(2)
6
Out
Output clock for bank B
CLKB2(2)
7
Out
Output clock for bank B
S2(3)
8
I N
Select input Bit 2
S1(3)
9
I N
Select input Bit 1
CLKB3(2)
10
Out
Output clock for bank B
CLKB4(2)
11
Out
Output clock for bank B
CLKA3(2)
14
Out
Output clock for bank A
CLKA4(2)
15
Out
Output clock for bank A
CLKOUT(2)
16
Out
Output clock, internal feedback on this pin
APPLICATIONS:
SDRAM
Telecom
Datacom
PC Motherboards/Workstations
Critical Path Delay Designs
REF
CLKA1
S2
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
CLKA2
GND
CLKB1
CLKOUT
CLKA4
GND
S1
VDD
CLKB2
CLKB3
CLKB4
CLKA3
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| IDT272401L10P | 制造商:Integrated Device Technology Inc 功能描述: |
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