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参数资料
| 型号： | IDT23S09T-1DCG |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 23S SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封装： | GREEN, SOIC-16 |
| 文件页数： | 3/6页 |
| 文件大小： | 53K |
| 代理商： | IDT23S09T-1DCG |
3
COMMERCIALTEMPERATURERANGE
IDT23S09T
2.5VZERODELAYCLOCKBUFFER,SPREADSPECTRUMCOMPATIBLE
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
Min.
Max.
Unit
VIL
Input LOW Voltage Level
—
0.7
V
VIH
Input HIGH Voltage Level
1.7
—
V
IIL
Input LOW Current
VIN = 0V
—
50
A
IIH
Input HIGH Current
VIN = VDD
—
100
A
VOL
Output LOW Voltage
Standard Drive, IOL = 8mA
—
0.3
V
VOH
Output HIGH Voltage
Standard Drive, IOH = -8mA
2
—
V
IDD_PD
Power Down Current
REF = 0MHz (S2 = S1 = H)
—
12
A
IDD
Supply Current
Unloaded Outputs at 66.66MHz, SEL inputs at VDD or GND
—
32
mA
SWITCHING CHARACTERISTICS
(1,2)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
t1
Output Frequency
15pF Load
10
—
133
MHz
Duty Cycle = t2
÷ t1
Measured at VDD/2, FOUT = 66.66MHz
40
50
60
%
t3
Rise Time
Measured between 0.7V and 1.7V
—
2.5
ns
t4
Fall Time
Measured between 0.7V and 1.7V
—
2.5
ns
t5
Output to Output Skew
All outputs equally loaded
—
250
ps
t6A
Delay, REF Rising Edge to CLKOUT Rising Edge(2) Measured at VDD/2
—
0
±350
ps
t6B
Delay, REF Rising Edge to CLKOUT Rising Edge(2) Measured at VDD/2 in PLL bypass mode
1
5
8.7
ns
t7
Device-to-Device Skew
Measured at VDD/2 on the CLKOUT pins of devices
—
0
700
ps
tJ
Cycle-to-Cycle Jitter
Measured at 66.66MHz, loaded outputs
—
200
ps
tLOCK
PLL Lock Time
Stable power supply, valid clock presented on REF pin
—
1
ms
NOTES:
1. REF Input has a threshold voltage of VDD/2.
2. All parameters specified with loaded outputs.
Symbol
Parameter
Min.
Max.
Unit
VDD
Supply Voltage
2.3
2.7
V
TA
OperatingTemperature(AmbientTemperature)
0
70
°C
CL
Load Capacitance 10MHz - 133MHz
—
15
pF
CIN
InputCapacitance
—
7
pF
OPERATING CONDITIONS
FUNCTION TABLE(1)
S2
S1
CLKA
CLKB
CLKOUT(2)
Output Source
PLL Shut Down
L
Tri-State
Driven
PLL
N
L
H
Driven
Tri-State
Driven
PLL
N
H
L
Driven
REF
Y
H
Driven
PLL
N
NOTES:
1. H = HIGH Voltage Level.
L = LOW Voltage Level
2. This output is driven and has an internal feedback for the PLL. The load on this ouput can be adjusted to change the skew between the REF and the output.
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