参数资料
型号: IDT54FCT162500ETEB
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 总线收发器
英文描述: CAP 4.7UF 25V 20% TANT SMD-6032-28 TR-7-PL SN100% LOWESR-600
中文描述: FCT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, CDFP56
封装: 0.635 MM PITCH, CERPACK-56
文件页数: 2/7页
文件大小: 123K
代理商: IDT54FCT162500ETEB
2
MILITARYANDCOMMERCIALTEMPERATURERANGES
IDT54/74FCT162500/AT/CT/ET
FASTCMOS18-BITREGISTEREDTRANSCEIVER
SSOP/ TSSOP/ TVSOP/ CERPACK
TOP VIEW
PIN CONFIGURATION
GN D
B 2
B 3
GN D
B 4
B 5
V CC
B 6
B 7
B 1
B 8
B 9
B 10
B 11
GN D
B 12
B 13
V CC
B 14
GN D
CL K A B
B 16
B 15
B 17
GN D
B 18
GN D
CL K B A
OE A B
LE A B
A 1
GN D
A 2
A 3
V CC
A 4
A 5
GN D
A 6
A 7
A 8
A 9
GN D
A 10
A 11
V CC
A 12
A 18
A 14
A 13
A 16
GN D
A 17
LE B A
A 15
OE B A
47
37
38
39
40
41
42
43
44
45
46
33
34
35
36
56
55
49
50
51
52
53
54
48
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
11
21
22
23
24
S O 56-1
S O 56-2
S O 56-3
E 56-1
29
30
31
32
25
26
27
28
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
Max
Unit
VTERM(2)
Terminal Voltage with Respect to GND
–0.5 to +7
V
VTERM(3)
Terminal Voltage with Respect to GND
–0.5 to VCC+0.5
V
TSTG
Storage Temperature
–65 to +150
°C
IOUT
DC Output Current
–60 to +120
mA
5v16-link
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
CAPACITANCE (TA = +25OC, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0V
3.5
6
pF
COUT
Output Capacitance
VOUT = 0V
3.5
8
pF
5v16-link
NOTE:
1. This parameter is measured at characterization but not tested.
PIN DESCRIPTION
Pin Names
Description
OEAB
A-to-B Output Enable Input
OEBA
B-to-A Output Enable Input (Active LOW)
LEAB
A-to-B Latch Enable Input
LEBA
B-to-A Latch Enable Input
CLKAB
A-to-B Clock Input (Active LOW)
CLKBA
B-to-A Clock Input (Active LOW)
A x
A-to-B Data Inputs or B-to-A 3-State Outputs
B x
B-to-A Data Inputs or A-to-B 3-State Outputs
NOTES:
1. A-to-B data flow is shown. B-to-A data flow is similar but uses
OEBA,
LEBA, and
CLKBA.
2. Output level before the indicated steady-state input conditions were
established.
3. Output level before the indicated steady-state input conditions were
established, provided that
CLKAB was LOW before LEAB went LOW.
4. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-impedance
↓ = HIGH-to-LOW Transition
FUNCTION TABLE(1,4)
Inputs
Outputs
OEAB
LEAB
CLKAB
Ax
Bx
LX
X
Z
HH
X
L
HH
X
H
HL
LL
HL
HH
HL
H
X
B(2)
HL
L
X
B(3)
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