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参数资料
| 型号： | IDT54FCT162511ATE |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 总线收发器 |
| 英文描述： | FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY |
| 中文描述： | FCT SERIES, 16-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, CDFP56 |
| 封装： | 0.635 MM PITCH, CERPACK-56 |
| 文件页数： | 1/10页 |
| 文件大小： | 180K |
| 代理商： | IDT54FCT162511ATE |
1
IDT54/74FCT162511AT/CT
FASTCMOS16-BITREGISTERED/LATCHEDTRANSCEIVER
MILITARYANDCOMMERCIALTEMPERATURERANGES
AUGUST 1999
1999
Integrated Device Technology, Inc.
DSC-2916/5
c
IDT54/74FCT162511AT/CT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FAST CMOS 16-BIT
REGISTERED/LATCHED
TRANSCEIVER WITH PARITY
DESCRIPTION:
The FCT162511AT/CT 16-bit registered/latched transceiver with parity
is built using advanced dual metal CMOS technology. This high-speed, low-
power transceiver combines D-type latches and D-type flip-flops to allow
data flow in transparent, latched, or clocked modes. The device has a parity
generator/checker in the A-to-B direction and a parity checker in the B-to-
A direction. Error checking is done at the byte level with separate parity bits
for each byte. Separate error flags exits for each direction with a single error
flag indicating an error for either byte in the A-to-B direction and a second
error flag indicating an error for either byte in the B-to-A direction. The parity
error flags are open drain outputs which can be tied together and/or tied with
flags from other devices to form a single error flag or interrupt. The parity
error flags are enabled by the
OExx control pins allowing the designer to
disable the error flag during combinational transitions.
The control pins LEAB, CLKAB, and
OEAB control operation in the A-
to-B direction while LEBA, CLKBA, and
OEBA control the B-to-A direction.
GEN/CHK is only for the selection of A-to-B operation. The B-to-A direction
is always in checking mode. The ODD/
EVEN select is common between
the two directions. Except for the ODD/
EVEN control, independent
operation can be achieved between the two directions by using the
corresponding control lines.
FUNCTIONAL BLOCK DIAGRAM
FEATURES:
0.5 MICRON CMOS Technology
Typical tsk(o) (Output Skew) < 250ps, clocked mode
Low input and output leakage ≤1A (max)
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
25 mil pitch SSOP, 19.6 mil pitch TSSOP, 15.7 mil pitch TVSOP
and 25 mil pitch CERPACK packages
Extended commercial range of –40°C to +85°C
VCC = 5V ±10%
Balanced Output Drivers:
±24mA (commercial)
±16mA (military)
Series current limiting resistors
Generate/Check, Check/Check modes
Open drain parity error allows wire-OR
GEN/C HK
Latch/
Register
Byte
Parity
Generator/
Checker
Latch/
Register
Byte
Parity
Checking
B0-15
A0-15
PA 1,2
PB 1,2
PE RB
LEA B
CLKA B
OEAB
OEBA
PE R A
LEB A
CLKB A
Parity, data
Parity, D ata
Data
(O pen Drain)
Parity
ODD/EVEN
16
18
2
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| IDT54FCT162511CTE | FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY |
| IDT54FCT162511AT | CAP 47UF 16V 20% TANT SMD-6032-28 TR-7-PL GOLD LOWESR-500 |
| IDT54FCT162511ATPA | FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT54FCT162511ATEB | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY |
| IDT54FCT162511ATPA | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY |
| IDT54FCT162511ATPAB | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY |
| IDT54FCT162511ATPF | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY |
| IDT54FCT162511ATPFB | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY |
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