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参数资料
| 型号： | IDT54FCT162511ATE |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 总线收发器 |
| 英文描述： | FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY |
| 中文描述： | FCT SERIES, 16-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, CDFP56 |
| 封装： | 0.635 MM PITCH, CERPACK-56 |
| 文件页数： | 5/10页 |
| 文件大小： | 180K |
| 代理商： | IDT54FCT162511ATE |
4
MILITARYANDCOMMERCIALTEMPERATURERANGES
IDT54/74FCT162511AT/CT
FASTCMOS16-BITREGISTERED/LATCHEDTRANSCEIVER
FUNCTION TABLE(1,4)
Inputs
Outputs
OEAB
LEAB
CLKAB
Ax
Bx
HX
X
Z
LH
X
L
LH
X
H
LL
↑
LL
↑
HH
LLL
X
B(2)
LL
H
X
B(3)
NOTES:
1. A-to-B data flow is shown. B-to-A data flow is similar but uses
OEBA,
LEBA, and CLKBA.
2. Output level before the indicated steady-state input conditions were
established.
3. Output level before the indicated steady-state input conditions were
established, provided that CLKAB was HIGH before LEAB went LOW.
4. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-Impedance
↑ = LOW-to-HIGH Transition
FUNCTION TABLE
(PARITY CHECKING) (1, 2, 3, 4)
A0 - A7 and PA1(5)
Number of inputs that are high
ODD/EVEN
PERB
1, 3, 5, 7 or 9
L
1, 3, 5, 7 or 9
H
H(6)
0, 2, 4, 6 or 8
L
H(6)
0, 2, 4, 6 or 8
H
L
FUNCTION TABLE
(PARITY GENERATION) (1, 2, 3, 4, 5)
A0 - A7
Number of inputs that are high
ODD/EVEN
PB1
1, 3, 5 or 7
L
H
1, 3, 5 or 7
H
L
0, 2, 4, 6 or 8
L
0, 2, 4, 6 or 8
H
NOTES:
1. Conditions shown are for
GEN/CHK = H, OEAB = L, OEBA = H.
2. A-to-B parity checking is shown. B-to-A parity checking is similar but uses
OEBA = L, OEAB = H and errors will be indicated on PERA.
3. In parity checking mode the parity bits will be transmitted unchanged along
with the corresponding data regardless of parity errors. (PB1 = PA1).
4. The response shown is for LEAB = H. If LEAB = L then CLKAB will control
as an edge triggered clock.
5. Conditions shown are for the byte A0-A7 and PA1. The byte A8-A15 and
PA2 is similiar.
6. The parity error flag
PERB is a combined flag for both bytes A0-A7 and
A8-A15. If a parity error occurs on either byte
PERB will go low. PERB
is an open drain output which must be externally pulled up to achieve a
logic HIGH.
NOTES:
1. Conditions shown are for
GEN/CHK = L, OEAB = L, OEBA = H.
2. A-to-B parity checking is shown. B-to-A is capable of parity checking while
A-to-B is performing generation. B-to-A will not generate parity.
3. The response shown is for LEAB = H. If LEAB = L then CLKAB will control
as an edge triggered clock.
4. Conditions shown are for the byte A0-A7. The byte A8-A15 is similiar but
will output the parity on PB2.
5. The error flag
PERB will remain in a high state during parity generation.
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| IDT54FCT162511ATPA | FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT54FCT162511ATEB | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY |
| IDT54FCT162511ATPA | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY |
| IDT54FCT162511ATPAB | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY |
| IDT54FCT162511ATPF | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY |
| IDT54FCT162511ATPFB | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY |
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