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参数资料
| 型号： | IDT54FCT162511ATEB |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 总线收发器 |
| 英文描述： | CAP 47UF 16V 20% TANT SMD-6032-28 TR-7-PL SN100% LOWESR-500 |
| 中文描述： | FCT SERIES, 16-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, CDFP56 |
| 封装： | CERPACK-56 |
| 文件页数： | 4/10页 |
| 文件大小： | 122K |
| 代理商： | IDT54FCT162511ATEB |
3
IDT54/74FCT162511AT/CT
FASTCMOS16-BITREGISTERED/LATCHEDTRANSCEIVER
MILITARYANDINDUSTRIALTEMPERATURERANGES
SSOP/ TSSOP/ CERPACK
TOP VIEW
PIN CONFIGURATION
GEN/CHK
B0
B1
GND
B2
B3
VCC
B4
B6
PB1
B7
PERB
GND
B8
B5
B9
B11
VCC
B12
B10
CLKAB
B14
B13
B15
GND
PB2
CLKBA
ODD/EVEN
OEAB
LEAB
PA1
GND
A0
A1
VCC
A2
A3
A5
A4
A6
A7
GND
A10
PERA
A8
VCC
A9
PA2
A12
A11
A14
GND
A15
LEBA
A13
OEBA
47
37
38
39
40
41
42
43
44
45
46
33
34
35
36
56
55
49
50
51
52
53
54
48
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
11
21
22
23
24
29
30
31
32
25
26
27
28
Symbol
Description
Max
Unit
VTERM(2)
Terminal Voltage with Respect to GND
–0.5 to 7
V
VTERM(3)
Terminal Voltage with Respect to GND
–0.5 to VCC+0.5
V
TSTG
Storage Temperature
–65 to +150
° C
IOUT
DC Output Current
–60 to +120
mA
ABSOLUTE MAXIMUM RATINGS(1)
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Output and I/O terminals for FCT162XXX.
Symbol
Parameter(1)
Conditions
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0V
3.5
6
pF
CI/O
I/O Capacitance
VOUT = 0V
3.5
8
pF
CO
Open Drain
VOUT = 0V
3.5
6
pF
Capacitance
CAPACITANCE (TA = +25°C, F = 1.0MHz)
PIN DESCRIPTION
Pin Names
Description
OEAB
A-to-B Output Enable Input (Active LOW)
OEBA
B-to-A Output Enable Input (Active LOW)
LEAB
A-to-B Latch Enable Input
LEBA
B-to-A Latch Enable Input
CLKAB
A-to-B Clock Input
CLKBA
B-to-A Clock Input
A x
A-to-B Data Inputs or B-to-A 3-State Outputs
B x
B-to-A Data Inputs or A-to-B 3-State Outputs
PERA
Parity Error (Open Drain) on A Outputs
PERB
Parity Error (Open Drain) on B Outputs
PAx(1)
A-to-B Parity Input, B-to-A Parity Output
PBx
B-to-A Parity Input, A-to-B Parity Output
ODD/
EVEN
Parity Mode Selection Input
GEN/CHK
A to B Port Generate or Check Mode Input
NOTE:
1. The PAx pin input is internally disabled during parity generation. This means that when
generating parity in the A to B direction there is no need to add a pull up resistor to
guarantee state. The pin will still function properly as the parity output for the B to A
direction.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT54FCT162511ATPA | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY |
| IDT54FCT162511ATPAB | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY |
| IDT54FCT162511ATPF | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY |
| IDT54FCT162511ATPFB | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY |
| IDT54FCT162511ATPV | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY |
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