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参数资料
| 型号： | IDT54FCT16952ETEB |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 总线收发器 |
| 英文描述： | FCT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, CDFP56 |
| 封装： | CERPACK-56 |
| 文件页数： | 6/7页 |
| 文件大小： | 73K |
| 代理商： | IDT54FCT16952ETEB |
6
MILITARYANDINDUSTRIALTEMPERATURERANGES
IDT54/74FCT16925AT/BT/CT/ET
FASTCMOS16-BITREGISTEREDTRANSCEIVER
Pulse
Generator
R T
D.U.T.
V CC
V IN
CL
V OUT
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCH R ONOUS C ONTROL
PRES ET
CLEA R
ETC.
SYNC HRON OUS C ON TROL
tSU
tH
tREM
tSU
tH
PRES ET
CLEA R
CLOC K ENABLE
ETC.
HIGH-LOW -HIGH
PULSE
LOW -HIGH-LOW
PULSE
tW
1.5V
SAM E PHASE
INPUT TRAN SITION
3V
1.5V
0V
1.5V
VOH
tPLH
OUTPUT
OPPOSITE P HASE
INPUT TRAN SITION
3V
1.5V
0V
tPLH
tPHL
VOL
CONTR OL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORM ALLY
LOW
OUTPUT
NORM ALLY
HIGH
SW ITCH
CLOSE D
SW ITCH
OPEN
VOL
0.3V
tPLZ
tPZL
tPZH
tPHZ
3.5V
0V
1.5V
ENAB LE
DISABLE
VOH
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuits for All Outputs
Enable and Disable Times
Set-up, Hold, and Release Times
Pulse Width
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
Open
SWITCH POSITION
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
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