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| 型号： | IDT5T93GL161PFGI8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 5T SERIES, LOW SKEW CLOCK DRIVER, 16 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64 |
| 封装： | GREEN, TQFP-64 |
| 文件页数： | 8/14页 |
| 文件大小： | 153K |
| 代理商： | IDT5T93GL161PFGI8 |
INDUSTRIALTEMPERATURERANGE
IDT5T93GL161
2.5VLVDS1:16GLITCHLESSCLOCKBUFFERTERABUFFERII
3
Symbol
Description
Max
Unit
VDD
Power Supply Voltage
–0.5 to +3.6
V
VI
Input Voltage
–0.5 to +3.6
V
VO
Output Voltage(2)
–0.5 to VDD +0.5
V
TSTG
Storage Temperature
–65 to +150
°C
TJ
Junction Temperature
150
°C
ABSOLUTE MAXIMUM RATINGS(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Not to exceed 3.6V.
Symbol
Parameter
Min
Typ.
Max.
Unit
CIN
Input Capacitance
——
3pF
CAPACITANCE(1) (TA = +25°C, F = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested
Symbol
Description
Min.
Typ.
Max.
Unit
TA
AmbientOperatingTemperature
–40
+25
+85
°C
VDD
InternalPowerSupplyVoltage
2.3
2.5
2.7
V
RECOMMENDED OPERATING RANGE
PIN DESCRIPTION
Symbol
I/O
Type
Description
A[1:2]
I
Adjustable(1,4) Clock input. A[1:2] is the "true" side of the differential clock input.
A[1:2]
I
Adjustable(1,4) Complementary clock inputs. A[1:2] is the complementary side of A[1:2]. For LVTTL single-ended operation, A[1:2] should be set to the
desiredtogglevoltageforA[1:2]:
3.3V LVTTL VREF = 1650mV
2.5V LVTTL VREF = 1250mV
G1
I
LVTTL
Gate control for differential outputs Q1andQ1 throughQ8 and Q8. WhenG1isLOW,thedifferential
outputs are active. When G1is HIGH, the differential outputs are asynchronously driven to the level designated by GL(2).
G2
I
LVTTL
Gate control for differential outputs Q9 and Q9 through Q16 and Q16. When G2is LOW, the differential outputs are active. When G2is
HIGH, the differential outputs are asynchronously driven to the level designated by GL(2).
GL
I
LVTTL
Specifies output disable level. If HIGH, "true" outputs disable HIGH and "complementary" outputs disable LOW. If LOW, "true"
outputsdisableLOWand"complementary"outputsdisableHIGH.
Qn
O
LVDS
Clockoutputs
Qn
O
LVDS
Complementaryclockoutputs
SEL
I
LVTTL
Reference clock select. When LOW, selects A2 and A2. When HIGH, selects A1 and A1.
PD
I
LVTTL
Power-down control. Shuts off entire chip. If LOW, the device goes into low power mode. Inputs and outputs are disabled. Both
"true" and "complementary" outputs will pull to VDD. Set HIGH for normal operation.(3)
FSEL
I
LVTTL
At a rising edge, FSEL forces select to the input designated by SEL. Set LOW for normal operation.
VDD
PWR
Power supply for the device core and inputs
GND
PWR
Ground
NOTES:
1. Inputs are capable of translating the following interface standards:
Single-ended 3.3V and 2.5V LVTTL levels
Differential HSTL and eHSTL levels
Differential LVEPECL (2.5V) and LVPECL (3.3V) levels
Differential LVDS levels
Differential CML levels
2. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt
pulses or be able to tolerate them in down stream circuitry.
3. It is recommended that the outputs be disabled before entering power-down mode. It is also recommended that the outputs remain disabled until the device completes power-
up after asserting PD.
4. The user must take precautions with any differential input interface standard being used in order to prevent instability when there is no input signal.
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