参数资料
型号: IDT6116SA15SOG8
厂商: IDT, Integrated Device Technology Inc
文件页数: 1/11页
文件大小: 0K
描述: IC SRAM 16KBIT 15NS 24SOIC
标准包装: 1,000
格式 - 存储器: RAM
存储器类型: SRAM - 异步
存储容量: 16K (2K x 8)
速度: 15ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 24-SOIC(0.295",7.50mm 宽)
供应商设备封装: 24-SOIC
包装: 带卷 (TR)
其它名称: 6116SA15SOG8
CMOS Static RAM
16K (2K x 8-Bit)
IDT6116SA
IDT6116LA
High-speed access and chip select times
Features
– Military: 20/25/35/45/55/70/90/120/150ns (max.)
– Industrial: 20/25ns (max.)
– Commercial: 15/20/25ns (max.)
Description
The IDT6116SA/LA is a 16,384-bit high-speed static RAM organized
as 2K x 8. It is fabricated using high-performance, high-reliability CMOS
technology.
Access times as fast as 15ns are available. The circuit also offers a
Low-power consumption
Battery backup operation
– 2V data retention voltage (LA version only)
Produced with advanced CMOS high-performance
technology
CMOS process virtually eliminates alpha particle soft-error
rates
Input and output directly TTL-compatible
Static operation: no clocks or refresh required
Available in ceramic 24-pin DIP, ceramic and plastic 24-pin Thin
Dip and 24-pin SOIC
Military product compliant to MIL-STD-833, Class B
reduced power standby mode. When CS goes HIGH, the circuit will
automatically go to, and remain in, a standby power mode, as long as CS
remains HIGH. This capability provides significant system level power and
cooling savings. The low-power (LA) version also offers a battery backup
data retention capability where the circuit typically consumes only 1μW to
4μW operating off a 2V battery.
All inputs and outputs of the IDT6116SA/LA are TTL-compatible. Fully
static asynchronous circuitry is used, requiring no clocks or refreshing for
operation.
The IDT6116SA/LA is packaged in 24-pin 300mil plastic DIP, 24-pin
600mil and 300mil ceramic DIP, or 24-lead gull-wing SOIC providing high
board-level packing densities.
Military grade product is manufactured in compliance to MIL-STD-883,
Class B, making it ideally suited to military temperature applications
demanding the highest level of performance and reliability.
Functional Block Diagram
A 0
V CC
A 10
I/O 0
ADDRESS
DECODER
INPUT
128 X 128
MEMORY
ARRAY
I/O CONTROL
GND
DATA
CIRCUIT
I/O 7
,
CS
OE
CONTROL
WE
CIRCUIT
1
3089 drw 01
FEBRUARY 2013
?2013 Integrated Device Technology, Inc.
DSC-3089/08
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