参数资料
型号: IDT7005L15PFG8
厂商: IDT, Integrated Device Technology Inc
文件页数: 2/21页
文件大小: 0K
描述: IC SRAM 64KBIT 15NS 64TQFP
标准包装: 750
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 64K (8K x 8)
速度: 15ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 64-LQFP
供应商设备封装: 64-TQFP(14x14)
包装: 带卷 (TR)
其它名称: 7005L15PFG8
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Description
The IDT7005 is a high-speed 8K x 8 Dual-Port Static RAM. The
IDT7005 is designed to be used as a stand-alone 64K-bit Dual-Port RAM
or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more
word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach
in 16-bit or wider memory system applications results in full-speed, error-
free operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by CE permits the on-chip circuitry of each port to enter
a very low standby power mode.
Pin Configurations (1,2,3)
11/16/01
INDEX
Military, Industrial and Commercial Temperature Ranges
Fabricated using CMOS high-performance technology, these de-
vices typically operate on only 750mW of power. Low-power (L) versions
offer battery backup data retention capability with typical power consump-
tion of 500μW from a 2V battery.
The IDT7005 is packaged in a ceramic 68-pin PGA, 68-pin quad
flatpack, 68-pin PLCC and a 64-pin thin quad flatpack, (TQFP). Military
grade product is manufactured in compliance with the latest revision of MIL-
PRF-38535 QML making it ideally suited to military temperature applica-
tions demanding the highest level of performance and reliability.
9
8
7
6 5
4
3
2
1 68 67 66 65 64 63 62 61
I/O 2L
I/O 3L
I/O 4L
I/O 5L
GND
10
11
12
13
14
60
59
58
57
56
A 5L
A 4L
A 3L
A 2L
A 1L
I/O 6L
I/O 7L
V CC
15
16
17
IDT7005J or F
J68-1 (4)
F68-1 (4)
55
54
53
A 0L
INT L
BUSY L
GND
I/O 0R
I/O 1R
I/O 2R
V CC
I/O 3R
I/O 4R
I/O 5R
I/O 6R
18
19
20
21
22
23
24
25
26
68 Pin PLCC / FLATPACK
Top View (5)
52
51
50
49
48
47
46
45
44
GND
M/S
BUSY R
INT R
A 0R
A 1R
A 2R
A 3R
A 4R
,
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
2738 drw 02
11/16/01
INDEX
I/O 2L
I/O 3L
I/O 4L
I/O 5L
GND
1
2
3
4
5
48
47
46
45
44
A 4L
A 3L
A 2L
A 1L
A 0L
I/O 6L
I/O 7L
V CC
6
7
8
7005PF
PN-64 (4)
43
42
41
INT L
BUSY L
GND
NOTES:
1. All V CC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J68-1 package body is approximately .95 in x .95 in x .12 in.
F68-1 package body is approximately .97 in x .97 in x .08 in.
PN64 package body is approximately 14mm x 14mm x 1.4mm.
GND
I/O 0R
I/O 1R
I/O 2R
V CC
I/O 3R
I/O 4R
I/O 5R
9
10
11
12
13
14
15
16
64-Pin TQFP
Top View (5)
40
39
38
37
36
35
34
33
M/ S
BUSY R
INT R
A 0R
A 1R
A 2R
A 3R
A 4R
.
4. This package code is used to reference the package diagram.
5. This text does not indicate oriention of the actual part-marking
6.42
2738 drw 03
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