参数资料
型号: IDT7005L15PFG8
厂商: IDT, Integrated Device Technology Inc
文件页数: 9/21页
文件大小: 0K
描述: IC SRAM 64KBIT 15NS 64TQFP
标准包装: 750
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 64K (8K x 8)
速度: 15ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 64-LQFP
供应商设备封装: 64-TQFP(14x14)
包装: 带卷 (TR)
其它名称: 7005L15PFG8
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage (5)
7005X15
Com'l Only
7005X17
Com'l Only
7005X20
Com'l, Ind
& Military
7005X25
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
t WC
t EW
t AW
Write Cycle Time
Chip Enable to End-of-Write (3)
Address Valid to End-of-Write
15
12
12
____
____
____
17
12
12
____
____
____
20
15
15
____
____
____
25
20
20
____
____
____
ns
ns
ns
t AS
Address Set-up Time
(3)
0
____
0
____
0
____
0
____
ns
t WP
t WR
t DW
Write Pulse Width
Write Recovery Time
Data Valid to End-of-Write
12
0
10
____
____
____
12
0
10
____
____
____
15
0
15
____
____
____
20
0
15
____
____
____
ns
ns
ns
t HZ
Output High-Z Time
(1,2)
____
10
____
10
____
12
____
15
ns
t DH
Data Hold Time
(4)
0
____
0
____
0
____
0
____
ns
t WZ
t OW
t SWRD
t SPS
Write Enable to Output in High-Z (1,2)
Output Active from End-of-Write (1,2,4)
SEM Flag Write to Read Time
SEM Flag Contention Window
____
0
5
5
10
____
____
____
____
0
5
5
10
____
____
____
____
0
5
5
12
____
____
____
____
0
5
5
15
____
____
____
ns
ns
ns
ns
2738 tbl 14a
7005X35
Com'l, Ind
& Military
7005X55
Com'l, Ind
& Military
7005X70
Military Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
t WC
t EW
t AW
Write Cycle Time
Chip Enable to End-of-Write (3)
Address Valid to End-of-Write
35
30
30
____
____
____
55
45
45
____
____
____
70
50
50
____
____
____
ns
ns
ns
t AS
Address Set-up Time
(3)
0
____
0
____
0
____
ns
t WP
t WR
t DW
Write Pulse Width
Write Recovery Time
Data Valid to End-of-Write
25
0
15
____
____
____
40
0
30
____
____
____
50
0
40
____
____
____
ns
ns
ns
t HZ
Output High-Z Time
(1,2)
____
15
____
25
____
30
ns
t DH
Data Hold Time
(4)
0
____
0
____
0
____
ns
Write Enable to Output in High-Z
t WZ
t OW
t SWRD
t SPS
(1,2)
Output Active from End-of-Write (1,2,4)
SEM Flag Write to Read Time
SEM Flag Contention Window
____
0
5
5
15
____
____
____
____
0
5
5
25
____
____
____
____
0
5
5
30
____
____
____
ns
ns
ns
ns
NOTES:
2738 tbl 14b
1. Transition is measured 0mV from Low or High-impedance voltage with load (Figure 2).
2. This parameter is guaranteed by device characterization but is not production tested.
3. To access RAM, CE = V IL , SEM = V IH . To access semaphore, CE = V IH and SEM = V IL . Either condition must be valid for the entire t EW time.
4. The specification for t DH must be met by the device supplying write data to the RAM under all operating conditions. Although t DH and t OW values will vary over voltage
and temperature, the actual t DH will always be smaller than the actual t OW .
5. 'X' in part number indicates power rating (S or L).
9
6.42
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