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参数资料
| 型号： | IDT7005S35G |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 12/21页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 64KBIT 35NS 68PGA |
| 标准包装： | 3 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 64K (8K x 8) |
| 速度： | 35ns |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 68-BPGA |
| 供应商设备封装： | 68-PGA（29.46x29.46） |
| 包装： | 托盘 |
| 其它名称： | 7005S35G |
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range (6)
7005X15
Com'l Only
7005X17
Com'l Only
7005X20
Com'l, Ind
& Military
7005X25
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/ S =V IH )
t BAA
t BDA
t BAC
t BDC
t APS
t BDD
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Access Time from Chip Enable High
Arbitration Priority Set-up Time (2)
BUSY Disable to Valid Data (3)
____
____
____
____
5
____
15
15
15
15
____
18
____
____
____
____
5
____
17
17
17
17
____
18
____
____
____
____
5
____
20
20
20
17
____
30
____
____
____
____
5
____
20
20
20
17
____
30
ns
ns
ns
ns
ns
ns
t WH
Write Hold After BUSY
(5)
12
____
13
____
15
____
17
____
ns
BUSY TIMING (M/S=V IL )
t WB
BUSY Input to Write (4)
0
____
0
____
0
____
0
____
ns
t WH
Write Hold After BUSY
(5)
12
____
13
____
15
____
17
____
ns
PORT-TO-PORT DELAY TIMING
t WDD
Write Pulse to Data Delay (1)
____
30
____
30
____
45
____
50
ns
t DDD
Write Data Valid to Read Data Delay
(1)
____
25
____
25
____
35
____
35
ns
2738 tbl 15a
7005X35
Com'l, Ind
& Military
7005X55
Com'l, Ind &
Military
7005X70
Military
Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/ S =V IH )
t BAA
t BDA
t BAC
t BDC
t APS
t BDD
t WH
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Acce ss Time from Chip Enable Low
BUSY Acce ss Time from Chip Enable High
Arbitration Priority Set-up Time (2)
BUSY Disable to Valid Date (3)
Write Hold After BUSY (5)
____
____
____
____
5
____
25
20
20
20
20
____
35
____
____
____
____
____
5
____
25
45
40
40
35
____
40
____
____
____
____
____
5
____
25
45
40
40
35
____
45
____
ns
ns
ns
ns
ns
ns
ns
BUSY TIMING (M/S=V IL )
Write Hold After BUSY
t WB
t WH
BUSY Input to Write (4)
(5)
0
25
____
____
0
25
____
____
0
25
____
____
ns
ns
PORT-TO-PORT DELAY TIMING
t WDD
Write Pulse to Data Delay (1)
____
60
____
80
____
95
ns
t DDD
Write Data Valid to Read Data Delay
(1)
____
45
____
65
____
80
ns
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY".
2. To ensure that the earlier of the two ports wins.
3. t BDD is a calculated parameter and is the greater of 0, t WDD – t WP (actual) or t DDD – t DW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention with port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part number indicates power rating (S or L).
12
6.42
2738 tbl 15b
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT7005S35GB | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 64KBIT 35NS 68PGA |
| IDT7005S35J | 功能描述:IC SRAM 64KBIT 35NS 68PLCC RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:45 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，异步 存储容量:128K（8K x 16） 速度:15ns 接口:并联 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:70V25S15PF |
| IDT7005S35J8 | 功能描述:IC SRAM 64KBIT 35NS 68PLCC RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:9M（256K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:71V67703S75PFGI |
| IDT7005S35JB | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM |
| IDT7005S35JG | 制造商:Integrated Device Technology Inc 功能描述: |
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