参数资料
型号: IDT7006S55PF
厂商: IDT, Integrated Device Technology Inc
文件页数: 15/20页
文件大小: 0K
描述: IC SRAM 128KBIT 55NS 64TQFP
标准包装: 45
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 128K (16K x 8)
速度: 55ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 64-LQFP
供应商设备封装: 64-TQFP(14x14)
包装: 托盘
其它名称: 7006S55PF
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM
Waveform of Interrupt Timing (1)
t WC
Military, Industrial and Commercial Temperature Ranges
ADDR "A"
t AS (3)
INTERRUPT SET ADDRESS (2)
t WR (4)
CE "A"
R/ W "A"
t INS (3)
INT "B"
2739 drw 17
t RC
ADDR "B"
INTERRUPT CLEAR ADDRESS (2)
t AS (3)
CE "B"
OE "B"
t INR (3)
INT "B"
2739 drw 18
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. See Interrupt Truth Table III.
3. Timing depends on which enable signal ( CE or R/ W ) is asserted last.
4. Timing depends on which enable signal ( CE or R/ W ) is de-asserted first.
Truth Tables
Truth Table III — Interrupt Flag (1,4)
Left Port
Right Port
R/ W L
CE L
OE L
A 13L -A 0L
INT L
R/ W R
CE R
OE R
A 13R -A 0R
INT R
Function
L
L
X
3FFF
X
X
X
X
X
L
(2)
Set Right INT R Flag
H
X
X
X
X
X
X
L
L
3FFF
(3)
Reset Right INT R Flag
X
X
X
X
L
(3)
L
L
X
3FFE
X
Set Left INT L Flag
H
X
L
L
3FFE
(2)
X
X
X
X
X
Reset Left INT L Flag
NOTES:
1. Assumes BUSY L = BUSY R = V IH .
2. If BUSY L = V IL , then no change.
3. If BUSY R = V IL , then no change.
4. INT R and INT L must be initialized at power-up.
15
6.42
2739 tbl 17
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