参数资料
型号: IDT7007L15JG
厂商: IDT, Integrated Device Technology Inc
文件页数: 10/21页
文件大小: 0K
描述: IC SRAM 256KBIT 15NS 68PLCC
标准包装: 9
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 256K (32K x 8)
速度: 15ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 68-LCC(J 形引线)
供应商设备封装: 68-PLCC(24x24)
包装: 管件
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage (5)
7007X15
Com'l Only
7007X20
Com'l & Ind
7007X25
Com'l, Ind
& Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
t WC
Write Cycle Time
15
____
20
____
25
____
ns
t EW
Chip Enable to End-of-Write
(3)
12
____
15
____
20
____
ns
t AW
t AS
t WP
t WR
t DW
Address Valid to End-of-Write
Address Set-up Time (3)
Write Pulse Width
Write Recovery Time
Data Valid to End-of-Write
12
0
12
0
10
____
____
____
____
____
15
0
15
0
15
____
____
____
____
____
20
0
20
0
15
____
____
____
____
____
ns
ns
ns
ns
ns
t HZ
Output High-Z Time
(1,2)
____
10
____
12
____
15
ns
t DH
Data Hold Time
(4)
0
____
0
____
0
____
ns
t WZ
t OW
t SWRD
t SPS
Write Enable to Output in High-Z (1,2)
Output Active from End-of-Write (1,2,4)
SEM Flag Write to Read Time
SEM Flag Contention Window
____
0
5
5
10
____
____
____
____
0
5
5
12
____
____
____
____
0
5
5
15
____
____
____
ns
ns
ns
ns
2940 tbl 13a
7007X35
Com'l, Ind
& Military
7007X55
Com'l, Ind
& Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
t WC
Write Cycle Time
35
____
55
____
ns
t EW
Chip Enable to End-of-Write
(3)
30
____
45
____
ns
t AW
t AS
t WP
t WR
t DW
Address Valid to End-of-Write
Address Set-up Time (3)
Write Pulse Width
Write Recovery Time
Data Valid to End-of-Write
30
0
25
0
15
____
____
____
____
____
45
0
40
0
30
____
____
____
____
____
ns
ns
ns
ns
ns
t HZ
Output High-Z Time
(1,2)
____
12
____
25
ns
t DH
t WZ
Data Hold Time (4)
Write Enable to Output in High-Z (1,2)
0
____
____
12
0
____
____
25
ns
ns
t OW
t SWRD
t SPS
Output Active from End-of-Write
SEM Flag Write to Read Time
SEM Flag Contention Window
(1,2,4)
0
5
5
____
____
____
0
5
5
____
____
____
ns
ns
ns
2940 tbl 13b
NOTES:
1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = V IL and SEM = V IH . To access semaphore, CE = V IH and SEM = V IL . Either condition must be valid for the entire t EW time.
4. The specification for t DH must be met by the device supplying write data to the RAM under all operating conditions. Although t DH and t OW values will vary over voltage
and temperature, the actual t DH will always be smaller than the actual t OW .
5. 'X' in part numbers indicates power rating (S or L).
10
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