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参数资料
| 型号： | IDT7007L15JG |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 13/21页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 256KBIT 15NS 68PLCC |
| 标准包装： | 9 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 256K (32K x 8) |
| 速度： | 15ns |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 68-LCC（J 形引线） |
| 供应商设备封装： | 68-PLCC（24x24） |
| 包装： | 管件 |
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range (6)
7007X15
Com'l Only
7007X20
Com'l & Ind
7007X25
Com'l, Ind
& Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/ S =V IH )
t BAA
t BDA
t BAC
t BDC
t APS
t BDD
t WH
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Acce ss Time from Chip Enable Low
BUSY Acce ss Time from Chip Enable High
Arbitration Priority Set-up Time (2)
BUSY Disable to Valid Data (3)
Write Hold After BUSY (5)
____
____
____
____
5
____
12
15
15
15
15
____
18
____
____
____
____
____
5
____
15
20
20
20
17
____
30
____
____
____
____
____
5
____
17
20
20
20
17
____
30
____
ns
ns
ns
ns
ns
ns
ns
BUSY TIMING (M/ S =V IL )
Write Hold After BUSY
t WB
t WH
BUSY Input to Write (4)
(5)
0
12
____
____
0
15
____
____
0
17
____
____
ns
ns
PORT-TO-PORT DELAY TIMING
t WDD
Write Pulse to Data Delay (1)
____
30
____
45
____
50
ns
t DDD
Write Data Valid to Read Data Delay
(1)
____
25
____
30
____
35
ns
2940 tbl 14a
7007X35
Com'l, Ind
& Military
7007X55
Com'l, Ind
& Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/ S =V IH )
t BAA
t BDA
t BAC
t BDC
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Acce ss Time from Chip Enable Low
BUSY Acce ss Time from Chip Enable High
____
____
____
____
20
20
20
20
____
____
____
____
45
40
40
35
ns
ns
ns
ns
Write Hold After BUSY
t APS
t BDD
t WH
Arbitration Priority Set-up Time
BUSY Disable to Valid Data (3)
(5)
(2)
5
____
25
____
35
____
5
____
25
____
40
____
ns
ns
ns
BUSY TIMING (M/ S =V IL )
Write Hold After BUSY
t WB
t WH
BUSY Input to Write (4)
(5)
0
25
____
____
0
25
____
____
ns
ns
PORT-TO-PORT DELAY TIMING
t WDD
Write Pulse to Data Delay (1)
____
60
____
80
ns
t DDD
Write Data Valid to Read Data Delay
(1)
____
45
____
65
ns
NOTES:
2940 tbl 14b
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/ S = V IH )".
2. To ensure that the earlier of the two ports wins.
3. t BDD is a calculated parameter and is the greater of 0, t WDD – t WP (actual) or t DDD – t DW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (S or L).
13
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT7007L15JG8 | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 256KBIT 15NS 68PLCC |
| IDT7007L15JI | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM |
| IDT7007L15PF | 功能描述:IC SRAM 256KBIT 15NS 80TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1,000 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，同步 存储容量:1.125M（32K x 36） 速度:5ns 接口:并联 电源电压:3.15 V ~ 3.45 V 工作温度:-40°C ~ 85°C 封装/外壳:256-LBGA 供应商设备封装:256-CABGA（17x17） 包装:带卷 (TR) 其它名称:70V3579S5BCI8 |
| IDT7007L15PF8 | 功能描述:IC SRAM 256KBIT 15NS 80TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1,000 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，同步 存储容量:1.125M（32K x 36） 速度:5ns 接口:并联 电源电压:3.15 V ~ 3.45 V 工作温度:-40°C ~ 85°C 封装/外壳:256-LBGA 供应商设备封装:256-CABGA（17x17） 包装:带卷 (TR) 其它名称:70V3579S5BCI8 |
| IDT7007L15PFB | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM |
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