参数资料
型号: IDT7007S35G
厂商: IDT, Integrated Device Technology Inc
文件页数: 1/21页
文件大小: 0K
描述: IC SRAM 256KBIT 35NS 68PGA
标准包装: 3
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 256K (32K x 8)
速度: 35ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 68-BPGA
供应商设备封装: 68-PGA(29.46x29.46)
包装: 托盘
其它名称: 7007S35G
HIGH-SPEED
32K x 8 DUAL-PORT
STATIC RAM
IDT7007S/L
True Dual-Ported memory cells which allow simultaneous
Features
reads of the same memory location
using the Master/Slave select when cascading more than
one device
High-speed access
– Military: 25/35/55ns (max.)
– Industrial: 20/25/35/55ns (max.)
– Commercial: 15/20/25/35/55ns (max.)
Low-power operation
– IDT7007S
Active: 850mW (typ.)
Standby: 5mW (typ.)
– IDT7007L
Active: 850mW (typ.)
Standby: 1mW (typ.)
IDT7007 easily expands data bus width to 16 bits or more
M/ S = H for BUSY output flag on Master,
M/ S = L for BUSY input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 5V (±10%) power supply
Available in 68-pin PGA and PLCC and a 80-pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
OE L
CE L
R/ W L
I/O 0L - I/O 7L
I/O
Control
I/O
Control
OE R
CE R
R/ W R
I/O 0R -I/O 7R
BUSY L
(1,2)
BUSY R
(1,2)
A 14L
A 0L
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A 14R
A 0R
15
15
INT L
SEM L
(2)
CE L
OE L
R/ W L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
M/ S
CE R
OE R
R/ W R
SEM R
INT R (2)
2940 drw 01
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY and INT outputs are non-tri-stated push-pull.
OCTOBER 2008
1
?2008 Integrated Device Technology, Inc.
DSC 2940/13
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