参数资料
型号: IDT7008S20J8
厂商: IDT, Integrated Device Technology Inc
文件页数: 13/19页
文件大小: 0K
描述: IC SRAM 512KBIT 20NS 84PLCC
标准包装: 200
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 512K (64K x 8)
速度: 20ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 84-LCC(J 形引线)
供应商设备封装: 84-PLCC(29.21x29.21)
包装: 带卷 (TR)
其它名称: 7008S20J8
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and BUSY (2,5) (M/ S = V IH ) (4)
t WC
ADDR "A"
MATCH
t WP
R/ W "A"
DATA IN "A"
t DW
VALID
t DH
ADDR "B"
t APS
(1)
MATCH
BUSY "B"
t WDD
t BDA
t BDD
DATA OUT "B"
NOTES:
t DDD
(3)
VALID
3198 drw 13
1. To ensure that the earlier of the two ports wins. t APS is ignored for M/ S = V IL (SLAVE).
2. CE L = CE R = V IL, refer to Chip Enable Truth Table.
3. OE = V IL for the reading port.
4. If M/ S = V IL (SLAVE), then BUSY is an input ( BUSY "A" = V IH and BUSY "B" = "don't care", for this example).
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
Timing Waveform of Write with BUSY (M/ S = V IL )
t WP
R/ W "A"
t WB (3)
BUSY "B"
t WH (1)
R/ W "B"
(2)
3198 drw 14
NOTES:
1. t WH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W "B" , until BUSY "B" goes HIGH.
3. t WB is only for the 'Slave' version.
13
6.42
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