参数资料
型号: IDT7008S20J8
厂商: IDT, Integrated Device Technology Inc
文件页数: 9/19页
文件大小: 0K
描述: IC SRAM 512KBIT 20NS 84PLCC
标准包装: 200
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 512K (64K x 8)
速度: 20ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 84-LCC(J 形引线)
供应商设备封装: 84-PLCC(29.21x29.21)
包装: 带卷 (TR)
其它名称: 7008S20J8
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range (6)
7008X15
Com'l Only
7008X20
Com'l
& Ind
7008X25
Com'l &
Military
7008X35
Com'l &
Military
7008X55
Com'l, Ind
& Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t RC
t AA
Read Cycle Time
Address Access Time
15
____
____
15
20
____
____
20
25
____
____
25
35
____
____
35
55
____
____
55
ns
ns
t ACE
Chip Enable Access Time
(4)
____
15
____
20
____
25
____
35
____
55
ns
t AOE
t OH
Output Enable Access Time
Output Hold from Address Change
____
3
10
____
____
3
12
____
____
3
13
____
____
3
20
____
____
3
30
____
ns
ns
t LZ
Output Low-Z Time
(1,2)
3
____
3
____
3
____
3
____
3
____
ns
t HZ
Output High-Z Time
(1,2)
____
10
____
12
____
15
____
15
____
25
ns
t PU
Chip Enable to Power Up Time
(2)
0
____
0
____
0
____
0
____
0
____
ns
t PD
t SOP
t SAA
Chip Disable to Power Down Time (2)
Semaphore Flag Update Pulse ( OE or SEM )
Semaphore Address Access Time
____
10
____
15
____
15
____
10
____
20
____
20
____
12
____
25
____
25
____
15
____
35
____
35
____
15
____
50
____
55
ns
ns
ns
3198 tbl 12
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage (6)
7008X15
Com'l Only
7008X20
Com'l
& Ind
7008X25
Com'l &
Military
7008X35
Com'l &
Military
7008X55
Com'l, Ind
& Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
t WC
Write Cycle Time
15
____
20
____
25
____
35
____
55
____
ns
t EW
Chip Enable to End-of-Write
(3)
12
____
15
____
20
____
30
____
45
____
ns
t AW
Address Valid to End-of-Write
12
____
15
____
20
____
30
____
45
____
ns
t AS
Address Set-up Time
(3)
0
____
0
____
0
____
0
____
0
____
ns
t WP
t WR
t DW
t HZ
Write Pulse Width
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time (1,2)
12
0
10
____
____
____
____
10
15
0
15
____
____
____
____
12
20
0
15
____
____
____
____
15
25
0
15
____
____
____
____
15
40
0
30
____
____
____
____
25
ns
ns
ns
ns
t DH
Data Hold Time
(5)
0
____
0
____
0
____
0
____
0
____
ns
Write Enable to Output in High-Z
t WZ
(1,2)
____
10
____
12
____
15
____
15
____
25
ns
t OW
t SWRD
t SPS
Output Active from End-of-Write
SEM Flag Write to Read Time
SEM Flag Contention Window
(1,2,5)
0
5
5
____
____
____
0
5
5
____
____
____
0
5
5
____
____
____
0
5
5
____
____
____
0
5
5
____
____
____
ns
ns
ns
NOTES:
3198 tbl 13
1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranted by device characterization, but is not production tested.
3. To access RAM, CE = V IL and SEM = V IH . To access semaphore, CE = V IH and SEM = V IL . Either condition must be valid for the entire t EW time.
4. To access RAM, CE = V IL and SEM = V IH . To access semaphore, CE = V IH and SEM = V IL .
5. The specification for t DH must be met by the device supplying write data to the RAM under all operating conditions. Although t DH and t OW values will vary over voltage
and temperature, the actual t DH will always be smaller than the actual t OW .
6. 'X' in part numbers indicates power rating (s or L).
9
6.42
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