参数资料
型号: IDT7014S25PFI
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: DRAM
英文描述: HIGH-SPEED 4K x 9DUAL-PORT STATIC RAM
中文描述: 4K X 9 DUAL-PORT SRAM, 25 ns, PQFP64
封装: TQFP-64
文件页数: 8/9页
文件大小: 89K
代理商: IDT7014S25PFI
IDT7014S
High-Speed 4K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
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The IDT7014 provides two ports with separate control, address,
and I/O pins that permt independent access for reads or writes to
any location in memory. It lacks the chip enable feature of CMOS Dual
Ports, thus it operates in active mode as soon as power is applied. Each
port has its own Output Enable control (
OE
). In the read mode, the port
s
OE
turns on the output drivers when set LOW. The user application should
avoid simultaneous write operations to the same memory location. There
is no on-chip arbitration circuitry to resolve write priority and partial data
fromboth ports may be written. READ/WRITE conditions are illustrated
in Table 1.
NOTE:
1. A
OL
- A
11L
is not equal to A
OR
- A
11R.
'H' = HIGH,'L' = LOW, 'X' = Don
t Care, and 'Z' = HIGH Impedance.
2528 drw 10
R/
t
WP
t
DW
DATA
OUT
ADDRESS
DATA
IN
t
AW
t
AS
(5)
t
WR
t
DH
t
OW
t
HZ(4)
(3)
(3)
t
WZ(4)
Left or Right Port
(1)
R/
D
0-8
Function
L
X
DATA
IN
Data written into memory
H
L
DATA
OUT
Data in memory output on port
X
H
Z
High-impedance outputs
2528 tbl 10
NOTES:
1. R/
W
must be HIGH during all address transitions.
2. t
WR
is measured from R/
W
going HIGH to the end of write cycle.
3. During this period, the I/O pins are in the output state, and input signals must not be applied.
4. Transition is measured 0mV fromthe Low or High-impedance voltage with the Output Test Load (Figure 2).
5. If
OE
is LOW during a R/
W
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WZ
+ t
DW
) to allow the I/O drivers to turn off data to be
placed on the bus for the required t
DW
. If
OE
is HIGH during an R/
W
controlled write cycle, this requirement does not apply and the write pulse can be as short as
the specified t
WP
.
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