参数资料
型号: IDT7015L12JG
厂商: IDT, Integrated Device Technology Inc
文件页数: 1/20页
文件大小: 0K
描述: IC SRAM 72KBIT 12NS 68PLCC
标准包装: 18
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 72K(8K x 9)
速度: 12ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 68-LCC(J 形引线)
供应商设备封装: 68-PLCC(24x24)
包装: 管件
HIGH-SPEED
8K x 9 DUAL-PORT
STATIC RAM
IDT7015S/L
True Dual-Ported memory cells which allow simultaneous
High-speed access
Features:
reads of the same memory location
– Commercial: 12/15/17/20/25/35ns (max.)
– Industrial: 20ns (max.)
M/ S = V IH for BUSY output flag on Master
M/ S = V IL for BUSY input on Slave
Busy and Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
– Military: 20/25/35ns (max.)
Low-power operation
– IDT7015S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7015L
Active: 750mW (typ.)
Standby: 1mW (typ.)
IDT7015 easily expands data bus width to 18 bits or more
between ports
Fully asynchronous operation from either port
TTL-compatible, single 5V (±10%) power supply
Available in ceramic 68-pin PGA, 68-pin PLCC, and an 80-
pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
using the Master/Slave select when cascading more than
one device
Functional Block Diagram
OE L
CE L
R/ W L
OE R
CE R
R/ W R
I/O 0L - I/O 8L
I/O
I/O
I/O 0R -I/O 8R
BUSY L
BUSY R
(1,2)
Control
Control
(1,2)
A 12L
A 0L
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A 12R
A 0R
13
13
INT L
INT R
NOTES:
SEM L
(2)
CE L
OE L
R/ W L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
M/ S
CE R
OE R
R/ W R
2954 drw 01
SEM R
(2)
1. In MASTER mode: BUSY is an output and is a push-pull driver
In SLAVE mode: BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull drivers.
OCTOBER 2008
1
?2008 Integrated Device Technology, Inc.
DSC 2954/8
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