参数资料
型号: IDT7015L12JG
厂商: IDT, Integrated Device Technology Inc
文件页数: 2/20页
文件大小: 0K
描述: IC SRAM 72KBIT 12NS 68PLCC
标准包装: 18
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 72K(8K x 9)
速度: 12ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 68-LCC(J 形引线)
供应商设备封装: 68-PLCC(24x24)
包装: 管件
IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM
Description:
The IDT7015 is a high-speed 8K x 9 Dual-Port Static RAM. The
IDT7015 is designed to be used as a stand-alone Dual-Port RAM or as
a combination MASTER/SLAVE Dual-Port RAM for 18-bit-or-more word
systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 18-
bit or wider memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
Pin Configurations (1,2,3)
11/16/01
INDEX
Military, Industrial and Commercial Temperature Ranges
feature controlled by CE permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 750mW of power.
The IDT7015 is packaged in a ceramic 68-pin PGA, a 64-pin PLCC
and an 80-pinTQFP (Thin Quad Flatpack). Military grade product is
manufactured in compliance with the latest revision of MIL-PRF-
38535 QML, making it ideally suited to military temperature applications
demanding the highest level of performance and reliability.
9
8
7
6 5
4
3
2
1 68 67 66 65 64 63 62 61
I/O 2L
I/O 3L
I/O 4L
I/O 5L
GND
10
11
12
13
14
60
59
58
57
56
A 5L
A 4L
A 3L
A 2L
A 1L
I/O 6L
I/O 7L
V CC
15
16
17
IDT7015J
J68-1 (4)
55
54
53
A 0L
INT L
BUSY L
GND
I/O 0R
I/O 1R
I/O 2R
V CC
I/O 3R
I/O 4R
I/O 5R
I/O 6R
18
19
20
21
22
23
24
25
26
68 Pin PLCC
Top View (5)
52
51
50
49
48
47
46
45
44
GND
M/ S
BUSY R
INT R
A 0R
A 1R
A 2R
A 3R
A 4R
,
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
2954 drw 02
Pin Names
NOTES:
1. All V CC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately .95 in x .95 in x .17 in.
4. This package code is used to reference the package diagram.
5. This text does not imply orientation of Part-marking.
Left Port
CE L
R/ W L
OE L
A 0L - A 12L
I/O 0L - I/O 8L
SEM L
INT L
BUSY L
Right Port
CE R
R/ W R
OE R
A 0R - A 12R
I/O 0R - I/O 8R
SEM R
INT R
BUSY R
M/ S
V CC
GND
Names
Chip Enable
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
2954 tbl 01
6.42
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