- 您现在的位置：买卖IC网 > PDF目录3991 > IDT7024S55G (IDT, Integrated Device Technology Inc)IC SRAM 64KBIT 55NS 84PGA PDF资料下载
参数资料
| 型号： | IDT7024S55G |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 17/22页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 64KBIT 55NS 84PGA |
| 标准包装： | 3 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 64K（4K x 16） |
| 速度： | 55ns |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 84-BPGA |
| 供应商设备封装： | 84-PGA（27.94x27.94） |
| 包装： | 托盘 |
| 其它名称： | 7024S55G |
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
Truth Table IV —
Address BUSY Arbritration
Military, Industrial and Commercial Temperature Ranges
Inputs
Outputs
CE L
X
H
X
L
CE R
X
X
H
L
A 0L -A 11L
A 0R -A 11R
NO MATCH
MATCH
MATCH
MATCH
BUSY L (1)
H
H
H
(2)
BUSY R (1)
H
H
H
(2)
Function
Normal
Normal
Normal
Write Inhibit (3)
2740 tbl 17
NOTES:
1. Pins BUSY L and BUSY R are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY X outputs on the IDT7024 are
push pull, not open drain outputs. On slaves, the BUSY asserted input internally inhibits write.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If t APS is not met, either BUSY L or BUSY R = LOW will result. BUSY L and BUSY R outputs cannot be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSY L outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSY R outputs are driving LOW regardless of actual logic level on the pin.
Truth Table V — Example of Semaphore Procurement Sequence (1,2,3)
Functions
No Action
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
D 0 - D 15 Left
1
0
0
1
1
0
1
1
1
0
1
D 0 - D 15 Right
1
1
1
0
0
1
1
0
1
1
1
Status
Semaphore free
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
2740 tbl 18
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7024.
2. There are eight semaphore flags written to via I/O 0 and read from all the I/O's. These eight semaphores are addressed by A0-A2.
3. CE = V IH , SEM = V IL , to access the Semaphores. Refer to the Semaphore Read/Write Control Truth Table.
Functional Description
The IDT7024 provides two ports with separate control, address and
I/O pins that permit independent access for reads or writes to any location
in memory. The IDT7024 has an automatic power down feature controlled
by CE . The CE controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected ( CE = V IH ).
When a port is enabled, access to the entire memory array is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
( INT L ) is asserted when the right port writes to memory location FFE
(HEX), where a write is defined as the CE = R/ W = V IL per the Truth Table
III. The left port clears the interrupt by access address location FFE access
when CE R = OE R = V IL, R/W is a "don't care". Likewise, the right port
interrupt flag ( INT R ) is asserted when the left port writes to memory location
FFF (HEX) and to clear the interrupt flag ( INT R ), the right port must access
the memory location FFF. The message (16 bits) at FFE or FFF is user-
defined, since it is an addressable SRAM location. If the interrupt function
17
6.42
相关PDF资料 |
PDF描述 |
|---|---|
| IDT7024S35G | IC SRAM 64KBIT 35NS 84PGA |
| IDT7024S25G | IC SRAM 64KBIT 25NS 84PGA |
| IDT7024S20G | IC SRAM 64KBIT 20NS 84PGA |
| IDT7024S17G | IC SRAM 64KBIT 17NS 84PGA |
| IDT7008L20JI | IC SRAM 512KBIT 20NS 84PLCC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT7024S55GB | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 64KBIT 55NS 84PGA |
| IDT7024S55J | 功能描述:IC SRAM 64KBIT 55NS 84PLCC RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:9M（256K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:71V67703S75PFGI |
| IDT7024S55J8 | 功能描述:IC SRAM 64KBIT 55NS 84PLCC RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:9M（256K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:71V67703S75PFGI |
| IDT7024S55JI | 功能描述:IC SRAM 64KBIT 55NS 84PLCC RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:45 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，异步 存储容量:128K（8K x 16） 速度:15ns 接口:并联 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:70V25S15PF |
| IDT7024S55JI8 | 功能描述:IC SRAM 64KBIT 55NS 84PLCC RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:9M（256K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:71V67703S75PFGI |
发布紧急采购，3分钟左右您将得到回复。