参数资料
型号: IDT7024S55PF8
厂商: IDT, Integrated Device Technology Inc
文件页数: 12/22页
文件大小: 0K
描述: IC SRAM 64KBIT 55NS 100TQFP
标准包装: 750
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 64K(4K x 16)
速度: 55ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 100-LQFP
供应商设备封装: 100-TQFP(14x14)
包装: 带卷 (TR)
其它名称: 7024S55PF8
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side (1)
t SAA
t OH
A 0 -A 2
VALID ADDRESS
VALID ADDRESS
SEM
t AW
t EW
t WR
t SOP
t AC E
t DW
I/O 0
DATA IN
VALID
DATA OUT
VALID (2)
R/ W
OE
t AS
t WP
Write Cycle
t DH
t SWRD
Read Cycle
t AOE
2740 drw 11
NOTES:
1. CE = V IH or UB & LB = V IH for the duration of the above timing (both write and read cycle).
2. “DATA OUT VALID” represents all I/O's (I/O 0 -I/O 15 ) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention (1,3,4)
A 0"A" -A 2"A"
MATCH
SIDE
(2)
SIDE
(2)
"A"
"B"
R/ W "A"
SEM "A"
A 0"B" -A 2"B"
R/ W "B"
SEM "B"
MATCH
t SPS
2740 drw 12
NOTES:
1. D 0R = D 0L = V IL , CE R = CE L = V IH , or both UB & LB = V IH , semaphore flag is released from both sides (reads as ones from both sides) at cycle start.
2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from R/ W A or SEM A going HIGH to R/ W B or SEM B going HIGH.
4. If t SPS is not satisfied, there is no guarantee which side will obtain the semaphore flag.
12
6.42
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