参数资料
型号: IDT7024S55PF8
厂商: IDT, Integrated Device Technology Inc
文件页数: 15/22页
文件大小: 0K
描述: IC SRAM 64KBIT 55NS 100TQFP
标准包装: 750
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 64K(4K x 16)
速度: 55ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 100-LQFP
供应商设备封装: 100-TQFP(14x14)
包装: 带卷 (TR)
其它名称: 7024S55PF8
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Waveform of BUSY Arbitration Controlled by CE Timing (1) (M/ S = V IH )
ADDR "A"
and "B"
CE "A"
CE "B"
t APS (2)
t BAC
ADDRESSES MATCH
t BDC
BUSY "B"
2740 drw 15
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing (1) (M/ S = V IH )
ADDR "A"
ADDR "B"
t APS
(2)
ADDRESS "N"
MATCHING ADDRESS "N"
t BAA
t BDA
BUSY "B"
2740 drw 16
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If t APS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range (1)
7024X15
Com'l Only
7024X17
Com'l Only
7024X20
Com'l , Ind
& Military
7024X25
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
t AS
t WR
t INS
t INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
Interrupt Reset Time
0
0
____
____
____
____
15
15
0
0
____
____
____
____
15
15
0
0
____
____
____
____
20
20
0
0
____
____
____
____
20
20
ns
ns
ns
ns
2740 tbl 15a
7024X35
Com'l &
Military
7024X55
Com'l, Ind
& Military
7024X70
Military Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
t AS
t WR
t INS
t INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
Interrupt Reset Time
0
0
____
____
____
____
25
25
0
0
____
____
____
____
40
40
0
0
____
____
____
____
50
50
ns
ns
ns
ns
NOTES:
1. 'X' in part number indicates power rating (S or L).
15
6.42
2740 tbl 15b
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