参数资料
型号: IDT70261S55PF
厂商: IDT, Integrated Device Technology Inc
文件页数: 2/19页
文件大小: 0K
描述: IC SRAM 256KBIT 55NS 100TQFP
标准包装: 45
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 256K(16K x 16)
速度: 55ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 100-LQFP
供应商设备封装: 100-TQFP(14x14)
包装: 托盘
其它名称: 70261S55PF
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt
Description
The IDT70261 is a high-speed 16K x 16 Dual-Port Static RAM. The
IDT70261 is designed to be used as a stand-alone Dual-Port RAM or as
a combination MASTER/SLAVE Dual-Port RAM for 32-bit-or-more word
systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32-
bit or wider memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
Pin Configurations (1,2,3)
11/16/01
Index
Industrial and Commercial Temperature Ranges
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by CE permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 750mW of power.
The IDT70261 is packaged in a 100-pin TQFP.
N/C
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1 75
N/C
N/C
N/C
N/C
I/O 10L
I/O 11L
I/O 12L
I/O 13L
GND
2
3
4
5
6
7
8
9
74
73
72
71
70
69
68
67
N/C
N/C
A 6L
A 5L
A 4L
A 3L
A 2L
A 1L
I/O 14L
I/O 15L
V CC
GND
I/O 0R
I/O 1R
I/O 2R
V CC
I/O 3R
I/O 4R
I/O 5R
I/O 6R
N/C
N/C
N/C
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
IDT70261PF
PN100-1 (4)
100-Pin TQFP
Top View (5)
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
A 0L
INT L
BUSY L
GND
M/ S
BUSY R
INT R
A 0R
A 1R
A 2R
A 3R
A 4R
A 5R
N/C
N/C
25
N/C
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
N/C
3039 drw 02
,
NOTES:
Pin Names
1. All V CC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
Left Port
CE L
R/ W L
OE L
A 0L - A 13L
I/O 0L - I/O 15L
SEM L
UB L
LB L
INT L
BUSY L
Right Port
CE R
R/ W R
OE R
A 0R - A 13R
I/O 0R - I/O 15R
SEM R
UB R
LB R
INT R
BUSY R
M/ S
V CC
GND
Names
Chip Enable
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Upper Byte Select
Lower Byte Select
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
3039 tbl 01
6.42
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