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参数资料
| 型号： | IDT7037L20PF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | DRAM |
| 英文描述： | x18 Dual-Port SRAM |
| 中文描述： | 32K X 18 DUAL-PORT SRAM, 20 ns, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 14/17页 |
| 文件大小： | 150K |
| 代理商： | IDT7037L20PF |
14
IDT7037L
High-Speed 32K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
BUSY
-
The IDT7037 provides two ports with separate control, address and
I/O pins that permt independent access for reads or writes to any location
in memory. The IDT7037 has an automatic power down feature controlled
by
CE
. The
CE
0
and CE
1
control the on-chip power down circuitry that
permts the respective port to go into a standby mode when not selected
(
CE
= HIGH). When a port is enabled, access to the entire memory array
is permtted.
5
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
(
INT
L
) is asserted when the right port writes to memory location 7FFE
(HEX), where a write is defined as
CE
R
= R/
W
R
= V
IL
per Truth Table
IV. The left port clears the interrupt through access of address location
7FFE when
CE
L
=
OE
L
= V
IL
, R/
W
is a "don't care". Likewise, the right
port interrupt flag (
INT
R
) is asserted when the left port writes to memory
location 7FFF (HEX) and to clear the interrupt flag (
INT
R
), the right port
must read the memory location 7FFF. The message (18 bits) at 7FFE or
7FFF is user-defined since it is an addressable SRAMlocation. If the
interrupt function is not used, address locations 7FFE and 7FFF are not
used as mail boxes, but as part of the randomaccess memory. Refer to
Table IV for the interrupt operation.
NOTES:
1. Pins
BUSY
L
and
BUSY
R
are both outputs when the part is configured as a master. Both are inputs when configured as a slave.
BUSY
outputs on the IDT7037 are
push-pull, not open drain outputs. On slaves the
BUSY
input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If t
APS
is not met, either
BUSY
L
or
BUSY
R
= LOW will result.
BUSY
L
and
BUSY
R
outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when
BUSY
L
outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when
BUSY
R
outputs are driving LOW regardless of actual logic level on the pin.
4. Refer to Chip Enable Truth Table.
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7037.
2. There are eight semaphore flags written to via I/O
0
and read fromall I/O's (I/O
0
-I/O
17
). These eight semaphores are addressed by A
0
-A
2
.
3.
CE
= V
IH
,
SEM
= V
IL
to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
$4$-3D//
B#
$4$-35D7.141E
!!"#
Inputs
Outputs
Function
CE
L
CE
R
A
OL
-A
14L
A
OR
-A
14R
BUSY
L
(1)
BUSY
R
(1)
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write
Inhibit
(3)
4838 tbl 17
Functions
D
0
- D
17
Left
D
0
- D
17
Right
Status
No Action
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
4838 tbl 18
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