参数资料
型号: IDT709099L9PFI
厂商: IDT, Integrated Device Technology Inc
文件页数: 13/16页
文件大小: 0K
描述: IC SRAM 1MBIT 9NS 100TQFP
标准包装: 6
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,同步
存储容量: 1M (128K x 8)
速度: 9ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 100-LQFP
供应商设备封装: 100-TQFP(14x14)
包装: 托盘
其它名称: 709099L9PFI
IDT709099L
High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(Flow-Through or Pipelined Outputs) (1)
t CYC2
CLK
t CH2
t CL2
ADDRESS
t SA
t HA
An
INTERNAL (3)
ADDRESS
An (7)
An + 1
An + 2
An + 3
An + 4
t SAD t HAD
ADS
CNTEN
t SD t HD
DATA IN
Dn
Dn + 1
Dn + 1
Dn + 2
Dn + 3
Dn + 4
WRITE
EXTERNAL
ADDRESS
WRITE WRITE
WITH COUNTER COUNTER HOLD
WRITE WITH COUNTER
4846 drw 17
Timing Waveform of Counter Reset (Pipelined Outputs) (2)
t CYC2
t CH2
t CL2
CLK
t SA t HA
ADDRESS (4)
An
An + 1
An + 2
INTERNAL (3)
ADDRESS
Ax (6)
0
1
An
An + 1
t SW t HW
R/ W
ADS
CNTEN
t SRST t HRST
CNTRST
DATA IN
t SD
t HD
D 0
DATA OUT (5)
Q 0
Q 1
Qn
.
COUNTER (6)
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS 1
READ
ADDRESS n
READ
ADDRESS n+1
4846 drw 18
NOTES:
1. CE 0 and R/ W = V IL ; CE 1 and CNTRST = V IH .
2. CE 0 = V IL ; CE 1 = V IH .
3. The "Internal Address" is equal to the "External Address" when ADS = V IL and equals the counter output when ADS = V IH .
4. Addresses do not have to be accessed sequentially since ADS = V IL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle.
7. CNTEN = V IL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’ Address is written
to during this cycle.
13
6.42
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