参数资料
型号: IDT70T3509MS133BPG
厂商: IDT, Integrated Device Technology Inc
文件页数: 1/23页
文件大小: 0K
描述: IC SRAM 36MBIT 133MHZ 256BGA
标准包装: 3
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,同步
存储容量: 36M(1M x 36)
速度: 133MHz
接口: 并联
电源电压: 2.4 V ~ 2.6 V
工作温度: 0°C ~ 70°C
封装/外壳: 256-BGA
供应商设备封装: 256-CABGA(17x17)
包装: 托盘
产品目录页面: 1254 (CN2011-ZH PDF)
其它名称: 70T3509MS133BPG
800-1379
HIGH-SPEED 2.5V
1024K x 36
SYNCHRONOUS
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
IDT70T3509M
True Dual-Port memory cells which allow simultaneous
Features:
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
access of the same memory location
High-speed data access
– Commercial: 4.2ns (133MHz)(max.)
– Industrial: 4.2ns (133MHz)(max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Interrupt Flags
Full synchronous operation on both ports
– 7.5ns cycle time, 133MHz operation (9.5Gbps bandwidth)
– 1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 133MHz
– Fast 4.2ns clock to data out
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output Mode
2.5V (±100mV) power supply for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
Includes JTAG functionality
Available in a 256-pin Ball Grid Array (BGA)
Common BGA footprint provides design flexibility over
seven density generations (512K to 36M-bit)
Green parts available, see ordering information
Functional Block Diagram
BE 3L
BE 2L
BE 1L
BE 0L
BE 3R
BE 2R
BE 1R
BE 0R
FT /PIPE L
1/0
0a 1a
a
0b 1b
b
0c 1c
c
0d 1d
d
1d 0d
d
1c 0c
c
1b 0b
b
1a 0a
a
1/0
FT /PIPE R
CE 0L
(2)
R/ W L
R/ W R
(2)
CE 0R
CE 1L
1
0
1/0
B B B B B B B B
W W W W W W W W
1
0
1/0
CE 1R
0 1 2 3 3 2 1 0
OE L
1d 0d 1c 0c 1b 0b 1a 0a
L L L L R R R R
Dout0-8_L
Dout0-8_R
Dout9-17_L
Dout9-17_R
Dout18-26_L
Dout18-26_R
Dout27-35_L
Dout27-35_R
0a 1a 0b 1b 0c 1c 0d 1d
OE R
,
FT /PIPE L
0/1
a b cd
dcba
0/1
FT /PIPE R
1024K x 36
MEMORY
ARRAY
I/O 0L - I/O 35L
CLK L
A 19L
Din_L
Din_R
I/O 0R - I/O 35R
CLK R
A 19R
,
A 0L
REPEAT L
ADS L
CNTEN L
Counter/
Address
Reg.
ADDR_L
ADDR_R
Counter/
Address
Reg.
A 0R
REPEAT R
ADS R
CNTEN R
TDI
TCK
CE 0 L
CE1L
INTERRUPT
LOGIC
CE 0 R
CE1R
TDO
JTAG
TMS
TRST
INT L
R/ W L
R/ W R
INT R
ZZ L
(1)
ZZ
CONTROL
LOGIC
ZZ R
(1)
5682 drw 01
NOTE:
1. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/ FT x and OPTx
and the sleep mode pins themselves (ZZx) are not affected during sleep mode.
2. See Truth Table I for Functionality.
?2009 Integrated Device Technology, Inc.
1
JANUARY 2009
DSC 5682/8
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