参数资料
型号: IDT70T3519S133BCI
厂商: IDT, Integrated Device Technology Inc
文件页数: 13/28页
文件大小: 0K
描述: IC SRAM 9MBIT 133MHZ 256BGA
标准包装: 6
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,同步
存储容量: 9M(256K x 36)
速度: 133MHz
接口: 并联
电源电压: 2.4 V ~ 2.6 V
工作温度: -40°C ~ 85°C
封装/外壳: 256-LBGA
供应商设备封装: 256-CABGA(17x17)
包装: 托盘
其它名称: 70T3519S133BCI
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Pipelined Operation
( FT /PIPE 'X' = V IH ) (1,2)
t CYC2
CLK
CE 0
t CH2
t CL2
t SC
t HC
t SC
t HC
(3)
CE 1
BE n
R/ W
t SB
t SW
t SA
t HB
t HW
t HA
t SB
(5)
t HB
ADDRESS
(4)
An
An + 1
An + 2
An + 3
(1 Latency)
t CD2
t DC
DATA OUT
t CKLZ
(1)
Qn
Qn + 1
t OHZ
t OLZ
Qn + 2
(5)
OE
(1)
t OE
5666 drw 05
Timing Waveform of Read Cycle for Flow-through Output
( FT /PIPE "X" = V IL ) (1,2,6)
t CYC1
CLK
CE 0
t CH1
t CL1
t SC
t HC
t SC
t HC
CE 1
t SB
t HB
(3)
BE n
R/ W
t SW t HW
t SA
t HA
t SB
t HB
ADDRESS
(4)
An
t CD1
An + 1
t DC
An + 2
An + 3
t CKHZ
DATA OUT
Qn
Qn + 1
Qn + 2 (5)
NOTES:
OE
(1)
t CKLZ
t OHZ
t OLZ
t OE
t DC
5666 drw 06
1. OE is asynchronously controlled; all other inputs depicted in the above waveforms are synchronous to the rising clock edge.
2. ADS = V IL , CNTEN and REPEAT = V IH .
3. The output is disabled (High-Impedance state) by CE 0 = V IH , CE 1 = V IL , BE n = V IH following the next rising edge of the clock. Refer to
Truth Table 1.
4. Addresses do not have to be accessed sequentially since ADS = V IL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
5. If BE n was HIGH, then the appropriate Byte of DATA OUT for Qn + 2 would be disabled (High-Impedance state).
6. "x" denotes Left or Right port. The diagram is with respect to that port.
13
6.42
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