参数资料
型号: IDT70T3519S166BF
厂商: IDT, Integrated Device Technology Inc
文件页数: 21/28页
文件大小: 0K
描述: IC SRAM 9MBIT 166MHZ 208FBGA
标准包装: 7
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,同步
存储容量: 9M(256K x 36)
速度: 166MHz
接口: 并联
电源电压: 2.4 V ~ 2.6 V
工作温度: 0°C ~ 70°C
封装/外壳: 208-LFBGA
供应商设备封装: 208-CABGA(15x15)
包装: 托盘
其它名称: 70T3519S166BF
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Collision Timing (1,2)
Both Ports Writing with Left Port Clock Leading
CLK L
t OFS
t SA
t HA
(4)
ADDRESS L
A 0
A 1
A 2
A 3
COL L
CLK R
t OFS
t COLS
(3)
t COLR
t SA
t HA
ADDRESS R
(4)
A 0
A 1
A 2
A 3
t COLS
t COLR
COL R
5666 drw 20
NOTES:
1. CE 0 = V IL , CE 1 = V IH .
2. For reading port, OE is a Don't care on the Collision Detection Logic. Please refer to Truth Table IV for specific cases.
3. Leading Port Output flag might output 3t CYC2 + t COLS after Address match.
4. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
Collision Detection Timing (3,4)
Cycle Time
Region 1 (ns)
(1)
t OFS (ns)
Region 2 (ns)
(2)
NOTES:
1. Region 1
5ns
6ns
7.5ns
0 - 2.8
0 - 3.8
0 - 5.3
2.81 - 4.6
3.81 - 5.6
5.31 - 7.1
Both ports show collision after 2nd cycle for Addresses 0, 2, 4 etc.
2. Region 2
Leading port shows collision after 3rd cycle for addresses 0, 3, 6, etc.
while trailing port shows collision after 2nd cycle for addresses 0, 2, 4 etc.
3. All the production units are tested to midpoint of each region.
4. These ranges are based on characterization of a typical device.
5666 tbl 13
Truth Table IV — Collision Detection Flag
Left Port
Right Port
CLK L
R/ W L (1)
H
H
L
L
CE L (1)
L
L
L
L
A 17L -A 0L (2)
MATCH
MATCH
MATCH
MATCH
COL L
H
L
H
L
CLK R
R/ W R (1)
H
L
H
L
CE R (1)
L
L
L
L
A 17R -A 0R (2)
MATCH
MATCH
MATCH
MATCH
COL R
H
H
L
L
Function
Both ports reading. Not a valid collision.
No flag output on either port.
Left port reading, Right port writing.
Valid collision, flag output on Left port.
Right port reading, Left port writing.
Valid collision, flag output on Right port.
Both ports writing. Valid collision. Flag
output on both ports.
NOTES:
1. CE 0 = V IL and CE 1 = V IH . R/ W and CE are synchronous with respect to the clock and need valid set-up and hold times.
2. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
21
6.42
5666 tbl 14
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