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参数资料
| 型号： | IDT70T3539MS133BCI8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 5/26页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 18MBIT 133MHZ 256BGA |
| 标准包装： | 1,000 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，同步 |
| 存储容量： | 18M（512K x 36） |
| 速度： | 133MHz |
| 接口： | 并联 |
| 电源电压： | 2.4 V ~ 2.6 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 256-LBGA |
| 供应商设备封装： | 256-CABGA（17x17） |
| 包装： | 带卷 (TR) |
| 其它名称： | 70T3539MS133BCI8 |
IDT70T3539M
High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM
Truth Table I—Read/Write and Enable Control
Industrial and Commercial Temperature Ranges
(1,2,3,4)
Byte 3
Byte 2
Byte 1
Byte 0
OE
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
H
X
CLK
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
X
CE 0
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
CE 1
X
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
BE 3
X
X
H
H
H
H
L
H
L
L
H
H
H
L
H
L
L
X
X
BE 2
X
X
H
H
H
L
H
H
L
L
H
H
L
H
H
L
L
X
X
BE 1
X
X
H
H
L
H
H
L
H
L
H
L
H
H
L
H
L
X
X
BE 0
X
X
H
L
H
H
H
L
H
L
L
H
H
H
L
H
L
X
X
R/ W
X
X
X
L
L
L
L
L
L
L
H
H
H
H
H
H
H
X
X
ZZ
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
I/O 27-35
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
D IN
High-Z
D IN
D IN
High-Z
High-Z
High-Z
D OUT
High-Z
D OUT
D OUT
High-Z
High-Z
I/O 18-26
High-Z
High-Z
High-Z
High-Z
High-Z
D IN
High-Z
High-Z
D IN
D IN
High-Z
High-Z
D OUT
High-Z
High-Z
D OUT
D OUT
High-Z
High-Z
I/O 9-17
High-Z
High-Z
High-Z
High-Z
D IN
High-Z
High-Z
D IN
High-Z
D IN
High-Z
D OUT
High-Z
High-Z
D OUT
High-Z
D OUT
High-Z
High-Z
I/O 0-8
High-Z
High-Z
High-Z
D IN
High-Z
High-Z
High-Z
D IN
High-Z
D IN
D OUT
High-Z
High-Z
High-Z
D OUT
High-Z
D OUT
High-Z
High-Z
MODE
Deselected –Power Down
Deselected –Power Down
All Bytes Deselected
Write to Byte 0 Only
Write to Byte 1 Only
Write to Byte 2 Only
Write to Byte 3 Only
Write to Lower 2 Bytes Only
Write to Upper 2 bytes Only
Write to All Bytes
Read Byte 0 Only
Read Byte 1 Only
Read Byte 2 Only
Read Byte 3 Only
Read Lower 2 Bytes Only
Read Upper 2 Bytes Only
Read All Bytes
Outputs Disabled
Sleep Mode
NOTES:
1. "H" = V IH, "L" = V IL, "X" = Don't Care.
2. ADS , CNTEN , REPEAT = X.
3. OE and ZZ are asynchronous input signals.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
5678 tbl 02
Truth Table II—Address Counter Control
(1,2)
Previous
Internal
L
Address
An
X
X
X
Internal
Address
X
An
An + 1
X
Address
Used
An
An + 1
An + 1
An
CLK
↑
↑
↑
↑
ADS
L (4)
H
H
X
CNTEN
X
(5)
H
X
REPEAT (6)
H
H
H
L (4)
I/O (3)
D I/O (n)
D I/O (n+1)
D I/O (n+1)
D I/O (n)
MODE
External Address Used
Counter Enabled —Internal Address generation
External Address Blocked —Counter disabled (An + 1 reused)
Counter Set to last valid ADS load
NOTES:
5678 tbl 03
1. "H" = V IH, "L" = V IL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/ W , CE 0 , CE 1 , BE n and OE .
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.
4. ADS and REPEAT are independent of all other memory control signals including CE 0 , CE 1 and BE n
5. The address counter advances if CNTEN = V IL on the rising edge of CLK, regardless of all other memory control signals including CE 0 , CE 1 , BE n.
6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS . This value is not set at power-up: a known location should be loaded
via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.
5
6.42
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