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参数资料
| 型号： | IDT70T3719MS133BBG |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | DRAM |
| 英文描述： | HIGH-SPEED 2.5V 256/128K x 72 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| 中文描述： | 256K X 72 DUAL-PORT SRAM, 15 ns, PBGA324 |
| 封装： | 19 X 19 MM, 1.40 MM HEIGHT, 1.76 MM PITCH, GREEN, BGA-324 |
| 文件页数： | 17/25页 |
| 文件大小： | 316K |
| 代理商： | IDT70T3719MS133BBG |
6.42
IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advanc e
(Flow-through or Pipelined Inputs)
(1)
Advanced
ADDRESS
An
t
CYC2
CLK
DATA
IN
R/
W
REPEAT
5687 drw 18
INTERNAL
(3)
ADDRESS
ADS
CNTEN
WRITE TO
ADDRESS
An
ADVANCE
WAn+1
ADVANCE
COUNTER
An+2
CHOLD
WAn+2
READ LAST
ADDRESS
An
DATA
OUT
t
SA
t
HA
An
,
t
SAD
t
HAD
t
SW
t
HW
t
SCN
t
HCN
t
SRPT
t
HRPT
t
SD
t
HD
t
CD1
An+1
An+2
An+2
An
An+1
An+2
An+2
D
0
D
1
D
2
D
3
An
An+1
An+2
An+2
ADVANCE
An+1
ADVANCE
READ
An+2
HOLD
CREAD
An+2
(4)
T iming Waveform of Counter Repeat
(2,6)
ADDRESS
An
CLK
DATA
IN
Dn
Dn + 1
Dn + 1
Dn + 2
ADS
CNTEN
t
CH2
t
CL2
t
CYC2
5687 drw 17
INTERNAL
(3)
ADDRESS
An
(7)
An + 1
An + 2
An + 3
An + 4
Dn + 3
Dn + 4
t
SA
t
HA
t
SAD
t
HAD
WRITE
COUNTER HOLD
WRITE WITH COUNTER
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
t
SD
t
HD
t
SCN
t
HC
N
,
NOTES:
1.
CE
0
,
BE
n
, and R/
W
= V
IL
; CE
1
and
REPEAT
= V
IH
.
2.
CE
0
,
BE
n
= V
IL
; CE
1
= V
IH
.
3. The "Internal Address" is equal to the "External Address" when
ADS
= V
IL
and equals the counter output when
ADS
= V
IH
.
4. No dead cycle exists during
REPEAT
operation. A READ or WRITE cycle may be coincidental with the counter
REPEAT
cycle: Address loaded by last valid
ADS
load will be accessed. For more information on
REPEAT
function refer to Truth Table II.
5.
CNTEN
= V
IL
advances Internal Address from‘An to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
6. For Pipelined Mode user should add 1 cycle latency for outputs as per timng waveformof read cycle for pipelined operations.
相关PDF资料 |
PDF描述 |
|---|---|
| IDT70T3719MS133BBGI | HIGH-SPEED 2.5V 256/128K x 72 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| IDT70T3719MS166BBG | HIGH-SPEED 2.5V 256/128K x 72 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| IDT70T3719MS166BBGI | HIGH-SPEED 2.5V 256/128K x 72 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| IDT70T3799M | HIGH-SPEED 2.5V 256/128K x 72 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| IDT70T3799MS133BBG | HIGH-SPEED 2.5V 256/128K x 72 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
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