参数资料
型号: IDT70T3719MS166BBGI
厂商: Integrated Device Technology, Inc.
英文描述: HIGH-SPEED 2.5V 256/128K x 72 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
中文描述: 高速与3.3V 2.5V的256/128K × 72 SYNCHRONOU S双,端口静态RAM或2.5V的接口
文件页数: 13/25页
文件大小: 316K
代理商: IDT70T3719MS166BBGI
6.42
IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
T iming Waveform of Left Port Write to Pipelined Right Port Read
(1,2,4)
Advanced
CLK
"A"
R/
W
"A
"
ADDRESS
"A"
DATA
IN"A"
CLK
"B"
R/
W
"B"
ADDRESS
"B"
DATA
OUT"B"
t
SW
t
HW
t
SA
t
HA
t
SD
t
HD
t
SW
t
HW
t
SA
t
HA
t
CO
(3)
t
CD2
MNO
VALID
MNO
MATCH
MATCH
VALID
5687 drw 09
t
DC
,
NOTES:
1.
CE
0
,
BE
n
, and
ADS
= V
IL
; CE
1
,
CNTEN
, and
REPEAT
= V
IH
.
2.
OE
= V
IL
for Port "B", which is being read from
OE
= V
IH
for Port "A", which is being written to.
3. If t
CO
< mnimumspecified, then data fromPort "B" read is not valid until following Port "B" clock cycle (ie, time fromwrite to valid read on opposite port will be
t
CO
+ 2 t
CYC2
+ t
CD2
). If t
CO
> mnimum then data fromPort "B" read is available on first Port "B" clock cycle (ie, time fromwrite to valid read on opposite port
will be t
CO
+ t
CYC2
+ t
CD2
).
4. All timng is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"
T iming Waveform with Port-to-Port Flow-T hrough Read
(1,2,4)
DATA
IN "A"
CLK
"B"
R/
W
"B"
ADDRESS
"A"
R/
W
"A"
CLK
"A"
ADDRESS
"B"
NO
MATCH
MATCH
NO
MATCH
MATCH
VALID
t
CD1
t
DC
DATA
OUT "B"
5687 drw 10
VALID
VALID
t
SW
t
HW
t
SA
t
HA
t
SD
t
HD
t
HW
t
HA
t
CD1
t
CO
t
DC
t
SA
t
SW
(3)
,
NOTES:
1.
CE
0
,
BE
n, and
ADS
= V
IL
; CE
1
,
CNTEN
, and
REPEAT
= V
IH
.
2.
OE
= V
IL
for the Right Port, which is being read from
OE
= V
IH
for the Left Port, which is being written to.
3. If t
CO
< mnimumspecified, then data fromPort "B" read is not valid until following Port "B" clock cycle (i.e., time fromwrite to valid read on opposite port will be
t
CO
+ t
CYC
+ t
CD1
). If t
CO
> mnimum then data fromPort "B" read is available on first Port "B" clock cycle (i.e., time fromwrite to valid read on opposite port will
be t
CO
+ t
CD1
).
4. All timng is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
相关PDF资料
PDF描述
IDT70T3799M HIGH-SPEED 2.5V 256/128K x 72 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
IDT70T3799MS133BBG HIGH-SPEED 2.5V 256/128K x 72 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
IDT70T3799MS133BBGI HIGH-SPEED 2.5V 256/128K x 72 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
IDT70T3799MS166BBG HIGH-SPEED 2.5V 256/128K x 72 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
IDT70T3799MS166BBGI HIGH-SPEED 2.5V 256/128K x 72 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
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