参数资料
型号: IDT70T3799MS166BBG
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: DRAM
英文描述: HIGH-SPEED 2.5V 256/128K x 72 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
中文描述: 128K X 72 DUAL-PORT SRAM, 12 ns, PBGA324
封装: 19 X 19 MM, 1.40 MM HEIGHT, 1.76 MM PITCH, GREEN, BGA-324
文件页数: 15/25页
文件大小: 316K
代理商: IDT70T3799MS166BBG
6.42
IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
T iming Waveform of Flow-T hrough Read-to-Write-to-Read (
OE
= V
IL
)
(2)
t
CYC1
Advanced
T iming Waveform of Flow-T hrough Read-to-Write-to-Read (
OE
Controlled)
(2)
t
CYC1
NOTES:
1. Output state (High, Low, or High-impedance) is determned by the previous cycle control signals.
2.
CE
0
,
BE
n, and
ADS
= V
IL
; CE
1
,
CNTEN
, and
REPEAT
= V
IH
.
3. Addresses do not have to be accessed sequentially since
ADS
= V
IL
constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
R/
W
ADDRESS
An
An +1
An + 2
An + 2
An + 3
An + 4
DATA
IN
Dn + 2
CE
0
CLK
5687 drw 13
Qn
DATA
OUT
CE
1
BE
n
t
CD1
Qn + 1
t
CH1
t
CL1
t
SD
t
HD
t
CD1
t
CD1
t
DC
t
CKHZ
NOP
Qn + 3
t
CD1
t
DC
t
SC
t
HC
t
SB
t
HB
t
SW
t
HW
t
SA
t
HA
READ
READ
t
CKLZ
(3)
(1)
t
SW
t
HW
WRITE
(5)
,
R/
W
ADDRESS
An
An +1
An + 2
t
SD
t
HD
An + 3
An + 4
An + 5
(3)
DATA
IN
Dn + 2
CE
0
CLK
5687 drw 14
Qn
DATA
OUT
CE
1
BE
n
t
CD1
t
CH1
t
CL1
t
CD1
t
DC
Qn + 4
t
CD1
t
DC
t
SC
t
HC
t
SB
t
HB
t
SW
t
HW
t
SA
t
HA
READ
WRITE
READ
t
CKLZ
(1)
Dn + 3
t
OHZ
t
SW
t
HW
OE
t
OE
,
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